Programmable Logic DesignLine Blog
"Good Grief Charlie Brown!" The guys and gals at Lattice Semiconductor have leapt into the fray with gusto and abandon (and some cool FPGA families)! The little rapscallions have just launched two new FPGA families: first we have the 90 nm LatticeSC (System Chip) family, which boasts high-channel-count SERDES blocks supporting 3.4 Gbps data rates, FPGA logic and memory blocks operating at 500 MHz, and embedded Structured ASIC blocks each equivalent to around 50,000 logic gates.
Meanwhile, the second-generation 90 nm EConomy Plus LatticeECP2 family cuts FPGA prices to under $0.50 per 1,000 Look-up Tables (LUTs) in high volume. Compared to its first-generation 130nm FPGAs, the new family doubles available density while reducing cost by 50%.
As Gerald S. (Jerry) Worchel, Principal Analyst for In-Stat's Semiconductor Logic Service says: "The LatticeSC should finally silence the skeptics: this is a very high performance FPGA that will compete aggressively with Virtex and Stratix devices for sockets. With the simultaneous announcement of the low cost LatticeECP2 devices, Lattice now has the breadth and depth of FPGA products to become the third force in the FPGA market."