Programmable Logic DesignLine Blog
As I pen these words, the FPGA 2006 conference is in progress. This looks like a real good place to be and I wish I were there (there are just too many things to do and too little time to do them all in; I have a theory that everyone is allocated a certain number of "time particles" each day, and some swine is stealing half of mine!).
As one example, there's an interesting paper entitled "Optimality study of logic synthesis for LUT-based FPGAs," being presented by Professor Jason Cong that I would love to hear. If you are at the conference and you attend this session, please let me know your thoughts on this topic (just email me at firstname.lastname@example.org).
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