Hopefully you saw the recent product announcement on Siloti from Novas. And I shall be a very disgruntled camper if you didn't find the time to peruse and ponder our How To Article on this very subject.
But on the off-chance you aren't up to date, let me summarize. One of the problems when debugging an FPGA design (or running an emulator) is gaining visibility into what's going on. There are ways to do this (embedding virtual logic analyzers, multiplexing internal signals onto output pins, etc.); but you can't watch every signal, and honing in on the problem area can be extremely time-consuming.
Even when you are running a software logic simulator, you run into much the same problems. That is, the simulator will run reasonably quickly so long as you aren't trying to capture lots of internal signals. If you do start to capture the activity on a lot of signals the simulator slows to a snail's pace. The alternative is to keep on re-simulating (capturing relatively few signals each time) and trying to focus in on the problem area.
And so we come to Siloti, which is named after the Russian-Ukrainian pianist, conductor and composer Alexander Il'yich Siloti or Ziloti (1863-1945) who was known to be something of a perfectionist. In a nutshell, Siloti (the one from Novas) analyzes your design and determines the key signals to monitor and capture (this is a fraction of the design's total signals). You then run your simulation or FPGA design or emulation capturing these signals. When you come to debug the design, Siloti uses the captured signals as the basis to re-create (synthesize) the missing signal/data values on-the-fly. What a GREAT idea!
Any thoughts you wish to share? Email me at firstname.lastname@example.org and tell me what you think. And, as usual, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.