Don’t panic, I'm still at the Multicore Expo 2006. In fact, I'm currently listening to a very interesting presentation by picoChip (www.picochip.com. These little scamps have a chip called a picoArray that contains several hundred CPU/DSP cores. And I now hear that picoArrays can be seamlessly connected together; picoChip say that they have a test configuration comprising 50,000 CPU/DSP cores (it makes your eyes water to think about it).
But I wanted to take a few minutes to highlight the recent snippet of news from AMI Semiconductor, who now have more than 3000 FPGA-to-ASIC Conversions to their credit. Let's assume that you are planning on prototyping your design in an FPGA and then – once you've got it working – you wish to convert it to an ASIC. How would you go about this?
One way would be to use one of the big FPGA vendors, who have their own FPGA-to-ASIC (or Structured ASIC) process. But the problem here is that the resulting ASICs can still be pretty expensive. The alternative is to use AMIS, who will take your FPGA design and convert it into an ASIC. This sounds easy if you say it quickly, but the process involves hairy tasks like transposing FPGA-centric intellectual property (IP) blocks into their ASIC-implementable counterparts.
But wait, there's more, because AMIS will also design the package for your ASIC so that the device is pin compatible with your original FPGA (i.e. pin/ball/column/whatever location, size, impedance, drive strength, signal slew, etc.). And the end result is said to be much cheaper than using an FPGA vendor's in-house ASIC/Structured ASIC approach (I think I heard the AMIS chips cost only 1/3 [or 1/5, my memory is not what it used to be] of the equivalent devices from an FPGA vendor).
Well, as far as I'm concerned, anyone who has performed 3000+ FPGA-to-ASIC conversions is a force to be reckoned with. Check out the AMIS website at www.amis.com
Any thoughts you wish to share? Email me at email@example.com and tell me what you think. And, as usual, if you haven’t already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.