As I mentioned in my previous blog, a few days ago I received an email from "EDA Analyst to the Stars" Gary Smith posing a number of essentially unanswerable questions, including the following:
- How big is a bacterium compared to a transistor on a modern silicon chip?
- How many die do you get on a 300 mm diameter wafer?
- What is the total length of the interconnect (poly-silicon and metal tracks) on a high-end silicon chip?
Well, I think we answered the first question to everyone's satisfaction yesterday (Click Here to discover the secrets of the ancients that have – until now – been hidden in the mists of time). So now let's proceed to question #2. . .
#2 How many die do you get on a 300 mm diameter wafer?
How many die are on a wafer? What sort of a question is this? It's like asking: "How long is a piece of string?" (Actually, there's an answer to this latter question, which is: "Twice as long as from the middle to the end!")
Hmmm, this obviously depends on the size of the die (the silicon chips themselves). As a starting point, the area of a circle is Pi × r^2 (that's Pi times the radius of the circle squared). So if we have a 300 mm diameter wafer, its area will be 3.142 × 150^2 = 3.142 × 22,500 = 70,695 square millimeters.
Now, let's assume that we can use the wafer right up to its edge (in reality there's a small border around the edge that we don't use). Let's also assume we are creating very small chips – not great big hairy System-on-Chip (SoC) devices, just itty-bitty little rascals intended to perform some relatively simple function. Suppose our die are each 1 mm × 1 mm = 1 square millimeter; some of the die will be cut short by the curve of the circle, so we might round things down to say 70,000 die (each 1mm × 1mm) on our 300 mm diameter wafer.
By comparison, what if our die were great big hairy beasts, each 20 mm × 20 mm = 400 square millimeters. In this case, we will only get 148 of these little scamps on a 300 mm wafer as shown below.
A 300 mm diameter wafer can hold 148 die
(assuming they are each 20 mm × 20 mm)
Of course, we are also going to lose some die to random defects, which will affect our yield (the number of good die compared to the total number we fabricate). Purely for the sake of these discussions, let's assume that we have 50 tiny inclusions (defects) in the waver itself – that these defects are randomly scattered across the surface of the wafer – that each defect will "kill" one of our die – and that these defects will be the only source of any failures.
In the case of our 1 mm × 1 mm die, this means that our failure rate will be 50 / 70,000 = ~0.0007 = 0.07%, so our yield will be 99.93% (hurray!). By comparison, in the case of our 20 mm × 20 mm die, our failure rate will be 50 / 148 = ~0.34 = 34%, so our yield falls to only 66% (yah, boo, hiss).
But just how big are typical die these days? In order to answer this poser, I called my old buddy Adam Traidman from Chip Estimate, whose InCyte chip estimation systems provide IC design teams, system architects, and management with the ability to visualize tradeoffs throughout the chip design flow.
Based on data culled from 50,000 chip estimations over the last 18 months, Adam was able to provide me with the following data:
Smallest die size:
0.683 mm × 0.683 mm at the 90 nm technology node
1.533 mm × 1.533 mm at the 65 nm technology node
Average die size
7.020 mm × 7.020 mm at the 90 nm technology node
2.130 mm × 2.130 mm at the 65 nm technology node
Biggest die size:
20.253 mm × 20.253 mm at the 65 nm technology node
This means that our 20 mm × 20 mm "guestimate" wasn't too far from the truth (honest, I did that part before I called Adam – just call me "Lucky Max"). Of course, that made me wonder as to the size of the largest die anyone has created since the dawn of history...
All I've been able to come up with so far is that the 2005 ITRS report says the maximum die back then was 23 mm × 26 mm (Click Here for more details). Also, from the Wikipedia, the die size of Intel's Montecito processor is 27.72 mm × 21.5 mm, which equates to a whopping 596 square millimeters (Click Here for more details).
Wow – that's pretty darn big! But is it the biggest die out there? Do you know something I don't? If so, please email me and I'll add it to my pile of "interesting facts" that always seem to come in useful when I least expect it.
OK, that's all for now, but don't forget to come back tomorrow when we will consider the answer to Gary's third question: "What is the total length of the interconnect (poly-silicon and metal tracks) on a high-end silicon chip?"
Questions? Comments? Feel free to email me – Clive "Max" Maxfield – at firstname.lastname@example.org). And, of course, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.