As you may recall, EDA Analytic Hero Gary Smith (the man, the myth, the legend) recently posed a few questions, including the following:
- How big is a bacterium compared to a transistor on a modern silicon chip?
- How many die do you get on a 300 mm diameter wafer?
- What is the total length of the interconnect (poly-silicon and metal tracks) on a high-end silicon chip?
We already answered the first and second questions in excruciating detail in Blog #1 and Blog #2 of this "mini-series", so all that remains is to tackle question #3 and wrestle it into submission...
#3 What is the total length of the interconnect (poly-silicon and metal tracks) on a high-end silicon chip?
Well, this is a bit of a tricky one isn't it? I mean, where do you go to find information like this? It's not like you can take the top off a chip package, pull out your trusty 12-inch ruler and start measuring things. I mean, we're talking about tracks so fine that you can't even see them with the naked eye!
Oh well, when in doubt, ask someone who has a clue. In this case, I asked Josh Jung Lee (President and CEO) and Sam Kim (Vice President) of Uniquify, which is a chip design services company focused on backend tools with a huge amount of expertise in design implementation.
As Josh told me, the hairiest design they've been involved in thus far was a 90 nm TSMC device comprising around 70 million gates and occupying 23 mm × 23 mm of silicon real estate. However, they were only involved in certain blocks for this chip so they don't have data for the entire device. On the bright side, they do have data for a variety of other designs as shown below:
"Good Grief Caruthers!" Take a look at the last two entries, which contain ~259 and ~224 meters of interconnect, respectively. If you average these out, the result is approximately 1.76 meters of interconnect for every square millimeter on the chip. This means that a really, REALLY hairy chip of say 24 mm × 24 mm could contain more than a kilometer of interconnect!
I have to say that this took me by surprise – if I had been pushed to make a guess, I think I would have come up with a value much smaller than this. What I would like to see now would be values for devices at the 65 nm and 45 nm technology nodes... if you have any information on this, please email me and share it.
But wait, there's more, because Bill Schweber, the editor of our sister site Planet Analog, has been avidly following this series (they don't let him out much), and he just emailed me to say:
Hi Max, I have a question: what is the total volume of silicon used to make chips – both the current annual amount and also the cumulative quantity since the invention of the silicon chip?
Arrgggghhh! "Curse you Red Baron!" Now I'm looking forward to another sleepless night trying to think of a way to determine the answer to this new poser... does anyone have any ideas?
Questions? Comments? Feel free to email me – Clive "Max" Maxfield – at email@example.com). And, of course, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.