Cool Beans - I just heard from someone who used a cunning trick from one of my articles to make his FPGA design work!
Well, I just had a real good start to my day, because I just heard from an FPGA designer who found something I'd written to be of use (and it's not often that happens – grin). Here's the gist of his message:
Hi Max, I just thought I'd let you know of a recent situation where an article of yours helped save me!
I am developing a video application on Altera's Cyclone II-Nios II evaluation board. I'm using the VGA port, loading images into the onboard SRAM, and reading them back to the video DAC.
I was writing some simple test patterns to the screen, but kept getting weird artifacts ... little dots in diagonal lines across the screen, and vertical lines where the color was slightly off. I double and triple checked my sync timings and the output of my address counters. Nothing seemed amiss...
Finally, I was looking at my address lines and one video output channel together on a scope. I noticed that a little blip on the video signal, corresponding to an artifact on the screen, also lined up with the falling edges of 6 or so address lines. A-hah, I thought, must be coupling between address and data buses, or ground bounce, or something line that! But how to fix such an issue when I was stuck with the hardware I already had? If only I could make sure I didn't have too many address lines changing at once...
Then I remembered your article on Gray codes from a while back. What if I used a Gray code address counter? The memory is SRAM, so it wouldn't care. But I was using the nice, simple binary counters for other things in my system as well. My solution? Put a binary-to-gray converter (as in your
Logic 101 – Gray Codes article) on my address outputs!
Voila, all the artifacts were gone!
Well, how cool. In fact I just did a quick search on the Programmable Logic DesignLine site to refresh my memory. In addition to the article mentioned above, we also have How to generate Gray Codes for non-power-of-2 sequences and Yet another Gray code conundrum (Part 1).
This latter "conundrum" article was particularly interesting. Do you recall it? The question was: "Is possible to generate a Gray code for a non-power-of-2 sequence that uses only consecutive addresses?"
As it happens, the answer is "Yes!" I received numerous responses and ideas to this first installment, but I just now realized that I never got around to writing Part 2 of this mini-series. Maybe I will find the time to do so over the coming Christmas holidays. In the meantime, if you have any thoughts on this topic, now would be a real good time to send them to me.
Questions? Comments? Feel free to email me – Clive "Max" Maxfield – at firstname.lastname@example.org). And, of course, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.