A few days ago I posted a new product announcement from OneSpin Solutions about their new Equivalence Checking for FPGAS that they claim to be "... the industry's first sequential equivalence checking solution dedicated to – and priced for – the FPGA market."
Well, shortly after I posted that piece, the following message wended its way across the Internet and "boing-ed" its way into my InBox:
Hi Max, my name is Aaik van der Poel, and I'm with Mentor overseeing a verity of applications, among which is Equivalence Checking.
I read your article about One-Spin's announcement of Equivalence Checking for FPGA's with interest. Through this mail I would like to make you aware of the fact that Mentor has had Equivalence Checking for FPGA's released as well.
Over the last couple of years we have added various technologies and now support Xilinx, Altera, AND Actel with our FormalPro-FPGA solution. The capabilities have been available to our ASIC users, however this summer we released a FPGA only package, priced for that market. One year time-based licenses start below the quoted OneSpin prices.
We also created an integration with Precision through a full ASCII based setup and helper file set. This greatly reduces Equivalence Verification setup times, and minimizes the chasing of false errors. Users have full access to this file and can switch off any guidance to satisfy their possible doubts.
We have seen an up-tick in interest since we released System Verilog support. As you know, EC is orders of magnitude faster to check full functionality without the need of an exhaustive testbench. We see a good combination usage between tools that help create the functionality like our Questa family, and FormalPro usage to make sure that functionality keeps tracking the initial specifications through the various optimizations and netlist changes that happen on the way from RTL to FPGA implementation.
Business Unit Manager
CED (Continuing Engineering Division)
Oooooh – interesting ... I wonder how OneSpin will respond...
Questions? Comments? Feel free to email me – Clive "Max" Maxfield – at firstname.lastname@example.org). And, of course, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.