Do you recall not-so-long ago when I posted an article an article about OneSpin's New Equivalence Checker dedicated to FPGA synthesis verification?
In a follow-up blog titled But are they equivalent?, I posted an email from Aaik van der Poewho oversees a variety of applications at Mentor, among which is Equivalence Checking.
In his email – amongst other things – Aaik noted that Mentor released a version of their Equivalence Checker priced for the FPGA market in the summer of 2007, and that one year time-based licenses for this package start below the quoted OneSpin prices.
Well ... I just heard back from OneSpin as follows:
Hello Max, my name is Michael Siegel. I am director of product marketing at OneSpin and would like to respond to the mail from Aaik van der Poel posted in your article 205200476.
ASIC Equivalence checking tools that have been enhanced to deal with FPGA designs have been around for quite some time now. However, the deployment of these tools has been slower than expected despite very clear customer demand. This is because these tools were not able to support the optimizations used by customers in their synthesis flows to achieve competitive performance, power and device utilization of their FPGA designs. In fact these tools required – and still require to our knowledge – the disabling of advanced synthesis optimizations such as retiming. In addition, they need information from synthesis side files – information that is known to be error-prone, resulting in false equivalence checking results and/or additional manual effort for workarounds.
The main differentiator of 360 EC-FPGA is its support of all sequential FPGA synthesis optimizations as confirmed by our customers. The 360 EC-FPGA solution verifies the optimized design "as is," without gate-level simulation, design modifications or design restrictions – such as disabling synthesis optimizations. Moreover, unlike the other equivalence checkers, it does not rely on synthesis "side files."
OneSpin's 360 EC-FPGA equivalence checking solution is the result of four years of research and development in sequential equivalence checking technology specifically to overcome these limitations.
Best regards, Michael Siegel
Did you just hear a "Boing"-type sound? I think that was the sound of the ball landing squarely back in Mentor's side of the court. I await Aaik's rejoinder in dread anticipation...
Questions? Comments? Feel free to email me – Clive "Max" Maxfield – at firstname.lastname@example.org). And, of course, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.