You have to hand it to those little PR/Marketing ragamuffins at Blue Pearl Software, because they seem to have a way to entice me into opening their email newsletters.
Their most recent offering promised to tell me: The Story of the Farmer and How He Got to Market Quickly with the Least Amount of Risk. Hmmm, I thought, what the heck can this have to do with EDA and FPGAs... (you see, they had me hooked already).
So, here's the way it goes (I'll give you the short version)...
A farmer lives on the east bank of a river. The market is on the west side of the river. The farmer has a goat and some cabbages that he wants to take to the market. One problem is that there's a mean old wolf who also lives on the east side of the river ... so the farmer wants to move the wolf to the west side of the river so that it won't cause any trouble (like eating his chickens) while he's away.
Are you with me so far?
Fortunately, the Farmer has a small boat. Unfortunately, the boat has room to carry only one of the wolf, goat, or box of cabbages besides himself.
If the farmer leaves the wolf and goat on the same bank, the wolf will eat the goat. If he leaves the goat and cabbages together, the goat will eat the cabbages. Fortunately, the wolf will not eat the cabbages.
So, what sequence of river crossings would allow the farmer to transfer his livestock and cabbages (and the wolf) safely to the west bank without anything being eaten?
Of course, I was poised to solve this poser when I saw that there was more. The newsletter continued as follows:
There are 2 ways to solve this puzzle.
- Look at the starting state, the goal state, and cycle through every single possibility until you find the correct answer, or, better yet...
- Use a combination of logic and intuition to quickly discover the intermediate states that will likely lead to success and rule out those which will not.
The point of all this is that the second approach is the way in which Blue Pearl Software validates timing exception constraints, allowing you to get to market faster with lower design risk.
Manually generated false and multi-cycle path exceptions often contain errors because of the use of wild-cards or incorrect designer assumptions. Ensuring that these exception paths are valid is a major problem.
Blue Pearl Software's Azure Timing Constraint Validation (applicable to both FPGA and ASIC designs) utilizes state space search technology, optimized for timing exception validation to formally explore the sequences of states that could activate exception paths.
How does it work?
"Good grief, Caruthers! That's jolly exciting. How does it work?" I cried! Fortunately, the newsletter was more than happy to oblige...
Rather than exhaustively traversing the billions of states in a typical design, Azure prunes the search space to focus only on the relevant state space.
If Azure determines that a path can be activated in a single or multiple cycles, it produces a vector sequence and generates a counter-example in the form of a test bench, which allows the accurate debugging of invalid timing constraints.
Azure offers early validation – at the RTL design stage. This offers several more key advantages: larger capacity, faster run times, and lower memory requirements.
Well, I'm sold ... I think I'll buy a copy for my dear old mom for Christmas (if I had a coconut for every time she's complained to me about problems with her timing constraints... I wouldn't have a lot of coconuts, but that's not the point...)
The point is that if you are interested in evaluating Azure to see how you can get to market with the lowest risk, you should contact the folks at Blue Pearl Software (www.BluePearlSoftware.com) right away.
FREE LUNCH and a Timing Closure Seminar
But wait, save the date (I'm a poet and I never knew-it) there's more, because the guys and gals at Blue Pearl Software will be holding a Timing Closure Lunch Seminar on Thursday, March 12, 2009 from 11:30am-1:30pm on in Santa Clara.
Registration is free, and lunch will be provided. It takes 30 seconds to sign up now and reserve your seat automatically. Or call 408-961-0121 x319. Map and directions will be provided upon RSVP.
Questions? Comments? Feel free to email me – Clive "Max" Maxfield – at firstname.lastname@example.org). And, of course, if you haven't already done so, don't forget to Sign Up for our weekly Programmable Logic DesignLine Newsletter.