On Sept. 16, EE Times will present a virtual conference on designing next-generation SoCs that promises to explore the challenges faced by developers of both ASIC- and FPGA-based SoCs.
On Sept. 16, EE Times will present a virtual conference on designing next-generation SoCs. The event promises to explore the challenges faced by developers of both ASIC- and FPGA-based SoCs.
Some of the scheduled highlights include panel discussions on the state of chip design economics, intellectual property, verification and integration between analog and digital design flows.
There are many reasons you might want to attend this event. One of them is that you can "be there" without leaving the comfort of your office, cubicle or home.
Another one, for FPGA users, is the focus on FPGA-based SoCs. I know that when I think about SoCs, I tend to think ASICs (sorry). But panelists and other participants scheduled to be on hand are planning to tell us how today's SoCs could just as well be FPGA-based.
As one of the event's chairs, I can tell you firsthand we've put a lot of time and effort into making sure this event is worthwhile for all attendees. We hope you can/will attend.
For more information on the event, as well as registration instructions, check out the event's homepage.