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EDA pundits envision more 'ASIC-like tools' for FPGAs

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re: EDA pundits envision more 'ASIC-like tools' for FPGAs
pitchMonk1   11/5/2009 5:29:15 PM
FPGAs seldom use static power islands.This is because the mapping functions become extremely complex to deal with islands. FPGAs need innovative techniques to lower power. Altera uses Vt scaling which can reduce leakage. In order to lower active power (that too significantly), you need sophisticated techniques. I recently helped an FPGA company to solve the power issue with some innovative techniques. If anyone is interested in knowing more, please leave your e-mail address and I can contact you. Thanks.

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