A pair of EDA pundits outlined some ways EDA would evolve, including getting more revenue from FPGA users.
At the International Conference on Computer-Aided Design this week, a couple of influential people from the world of EDA hosted a sort of roundtable discussion on EDA and how it needs to change to be successful in 2020. [Random note: for many, many people's sake, let's hope EDA can find a way to be successful prior to 2020]. The conversation turned more than once to FPGAs.
The hosts were Jim Hogan, a former bigwig at Cadence Design Systems turned venture capitalist, and Paul McLellan, a veteran EDA exec and consultant and author of the blog EDA Graffiti. The pair outlined a number of now-familiar challenges facing the broader semiconductor industry: fragmenting markets, steeper adoption ramps, increasing design costs and fewer markets that demand high volumes of 150 to 200 million chips.
Xilinx President and CEO Moshe Gavrielov and others in programmable logic use these exact same trends to support their thesis: that FPGAs will reign supreme because there are fewer and fewer market opportunities where doing an ASIC or ASSP makes economic sense.
Hogan and McLellan used June-quarter data from Xilinx and Altera to demonstrate that, combined, the companies generate 40 percent of total FPGA revenue from "new" products. [Random note #2: This is category defined by Xilinx as Virtex-5 and -6, and Spartan-6, -3A and -3E; for Altera it's Stratix II, III and IV, Arria GX, II GX, Cyclone II and III, Max II and HardCopy and HardCopy II devices]. Hogan and McClellan said the "new" category represents about 12 percent of 90,000 projected total design starts.
Hogan interprets this to mean that 12 percent of the 90,000 FPGA starts are of technology sufficiently complex to require advanced ASIC design tools. And Hogan said FPGAs of the not-so-distant future will add more hard cores and other complex innovations that will make them comparable to ASSPs in cost and performance.
"You can't deal with that complexity without ASIC-like tools," Hogan said.
McLellan said FPGAs will need to employ more sophisticated design techniques to reduce power consumption and, presumably, will need more sophisticated tools to do so.
"As far as I know, FPGAs don't have lots of power islands and that sort of thing," McLellan said. "But they're going to have to start moving in that direction."
Neither Hogan nor McLellan suggested that more revenue from the FPGA world would by itself cure what ails EDA. But Hogan did say EDA was "right on the cusp" of generating more money from the space, which has traditionally seen limited offerings from EDA vendors since FPGA vendors offer their own low-cost tools optimized for their particular architectures.
[Random note #3: What did they prescribe for EDA? "Software signoff" (defined by McLellan as taking software written in C and CC++ and synthesizing parts of it into FPGAs and compiling the rest into binary to run on processors in the FPGA), a move to system-level design and an emphasis on tools and services that optimize designs. You can read more about the presentation on EDA Graffiti.]
[Random note #4: Is it just me or does everyone have a different suggestion for what EDA needs to do to evolve?]
Still, it's clear they see room for more third-party design tools aimed at FPGA users.
"Since a good portion of SoCs are using FPGAs as a simulation accelerator or emulator, I expect the tool budgets will now get interesting," Hogan said in an email exchange following the presentation.