There were several interesting FPGA-related papers presented at the 2009 International Conference on Computer-Aided Design last week in San Jose.
There were some interesting FPGA-related papers presented at the 2009 International Conference on Computer-Aided Design (ICCAD) last week in San Jose, Calif.
The first, and probably most interesting, came from a group of researchers at the University of California-Los Angeles (UCLA). Their paper, titled "IPR: In-Place Reconfiguration for FPGA Fault Tolerance," describes a technique for reducing soft errors in FPGAs at the logic design synthesis stage.
The UCLA researchers developed a fault-tolerant logic resynthesis algorithm which they said decreased the circuit fault rate while preserving functionality and topology of the LUT-based logic network. This resynthesis algorithm can be applied post-layout and without changes to the physical design, they said.
In the research, this in-place reconfiguration (IPR) algorithm was combined with ROSE, another fault-tolerant logic resynthesis algorithm that was described at the 2008 ICCAD, to demonstrate a reduced fault rate and increased mean-time-between-failures compared to the academic technology mapper known as Berkeley ABC, according to the paper.
The UCLA researchers said they were encouraged by the results of their work so far and plan to further explore and develop the IPR technology.
"IPR: In-Place Reconfiguration for FPGA Fault Tolerance," by UCLA's Zhe Feng, Lei He and Rupak Majumdar, was a nominee for the show's best paper award.
(The honors, by the way, were split between a group from the University of Karlsruhe for "TAPE: Thermal-Aware Agent-Based Power Economy for Multi/Many-Core Architectures" and a group from China's National University of Defense Technology and Sweden's Royal Institute of Technology for "From 2D to 3D NOCs: A Case Study on Worst-Case Communication Performance.")
Among some of the other papers of interest to FPGA developers presented at ICCAD was a paper by researchers from the Georgia Institute of Technology and Case Western Reserve University titled "A Circuit-Software Co-Design Approach for Improving EDP in Reconfigurable Frameworks."
More information on the recent ICCAD can be found here.