IBC is the leading global tradeshow for professionals engaged in the creation, management and delivery of broadcasting media and entertainment. The event's unparalleled exhibition and agenda setting conference encompass the very latest developments in broadcasting, mobile TV, IPTV, digital signage and R&D making it essential for everyoneís understanding of the industry and its future.
Xilinx has just announced its participation at IBC 2011 in Amsterdam, from September 8-13, at the RAI Exhibition and Congress Centre, Stand #10.D25, Hall 10.
Xilinx will demonstrate programmable platforms that assist broadcast equipment makers in building systems capable of delivering content over traditional SD/HD/3G-SDI and AES3 connections as well as bridging to video over IP networks whilst maintaining highest possible video quality.
In-stand demonstrations will highlight the implementation and adoption of emerging IP network technologies, the removal of external Voltage-Controlled Crystal Oscillators (VCXOs) for SDI reference clocks, low power consumption 28nm devices, IP cores for real-time 1080p60 and 4K video processing, and AVC-I codecs on the Virtex-6 device for reduction of bandwidth and storage requirements without sacrificing video quality.
Implement and Adapt to Emerging Network Technologies
Xilinx will demonstrate the SMPTE 2022-5/-6 intellectual property core, which enables the adoption of lower cost Ethernet networks for transporting uncompressed video, support for up to 6x HD-SDI or 3x 3G-SDI video interfaces with excellent jitter performance, and support for SMPTE 2022-5/-6 Video over IP designs. With this demo, Xilinx is showcasing this intellectual property core running on the Virtex-6 FPGA as well as the Targeted Design Platform concept supported by the SDI interface on the FPGA Mezzanine Card (FMC) standard and its ecosystem supported by Xilinx.Remove External VCXOs for SDI Reference Clocks
Debuting at IBC, attendees can see a demonstration of how customers can remove the VCXO components from their multichannel SDI designs through FPGA integration, resulting in a significant bill of materials reduction (up to $20 per video output channel). Using capabilities built into Xilinx transceivers, the reference design allows all transmit SERDES to be used with unique clock rates, decouples FPGA fabric noise from the SERDES, performs with low jitter, and uses no extra power. The VCXO removal reference design is available for Virtex-6 FPGAs, next generation 7 series FPGAs and Zynq Extensible Processing Platforms.Lowering Power and Heat in Broadcast Applications with 7 Series FPGAs
By demonstrating SDI support on the Kintex-7 FPGA, Xilinx will show how cost and power can be reduced by up to 50 percent without sacrificing performance compared to previous generation FPGAs. The industry's first 28nm FPGA enables smooth migration of designs from previous generation Virtex-6 FPGAs and across the 7 series FPGAs. IP Cores for Real-Time 1080p60 and 4K Video Processing
Xilinx's Real-Time Video Engine Targeted Design Platform running on Virtex-6 FPGAs and Spartan-6 FPGAs illustrate the use of the Targeted Design Platforms for prototyping and implementing video processing chains in broadcast equipment. The Targeted Design Platform can be used for new video designs or to expand the features set of existing designs.Reduce Video Bandwidth and Storage Requirements Without Sacrificing Video Quality
Xilinx Alliance Member Vanguard Software Solutions will also exhibit their H.264/AVC-I and AVC-Ultra Video Codec core, which will show broadcast equipment manufacturers how to quickly and easily integrate AVC-I Class50 and Class100 and AVC-Ultra (up to 300 Mbps) into their broadcast systems, which ultimately leads to lower cost of using hard-disk over tape by enabling smaller file sizes which further drives the need for SMPTE 2022-5/-6.
for more information.
If you found this article to be of interest, visit Programmable Logic Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter Ė just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).