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How It Was: Programmable Logic

Clive Maxfield
11/10/2011 06:45 PM EST

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DrJeff1
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Don't forget PLPL
DrJeff1   6/15/2017 5:47:42 PM
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This has brought back some memories.

I became involved with PALs and early PLDs in the late eighties whilst working on a design for my PhD at Southampton University.


I was in the position which sadly a lot of engineers find themselves in; I was well read on devices and equipment but had absolutely no money to use them. I really had to use programmable logic to implement the number of processing engines my system required, but the price of a programmer (>£1,000) was way above the budget of the department. Moreover, the offerings of ABEL and CUPL were only available to run on the emerging 8086 variety of PCs. Our department had 68000 based workstations internally developed for microelectronics CAD and a PC (again > £1,000) was way beyond my personal budget.

This needed me to find both hardware and software from somewhere else to enable me to continue my project.

Fortunately I had previously worked for Dataman Designs (of S3 fame) as a principal engineer and had good knowledge of device programming. I obtained a contract with them to do part time work to add PLD programming adaptors to the S3 and S4 EPROM programmers. Using their industry position I was able to obtain programming information (the all important JEDEC fuse map) to the Altera EP300, EP600, EP900 and EP1800 parts, also ICT's 18CV8 and 22V10. These gave Dataman useful additions to their affordable programmer range and gave me prototype programming hardware to use on my PhD project.

This left the software tools. Whilst I could have persued PALASM; it was more akin to an assembler, with direct links between the equations and the corresponding fuse map. I needed something more like a silicon compiler; which gave structure to logic statements. I had heard about ABEL and CUPL, but as these were expensive tools way out of the reach of a mere designer like me and I couldn't evaluate them properly anyway (as I had no access to an 8086 PC). I kept looking and AMD had something called PLPL - shown as examples in their databooks looked like it might work as it converted logic constructions to fuse maps for the 22V10 and smaller PAL devices. It was offered free of charge, but for PC usage only!

I contacted AMD, and explained my situation, to my astonishment they said that they couldn't help directly, but would a copy of the source code to PLPL me useful to me? I was astonished and will be eternally grateful to their selfless act of philanthropy. It was sent to me "as is" as a set of 'C' source files without warrnaty for my personal use. I had no formal training in software, and after obtaining a 'C' compiler for our 68000 workstations, set to task on getting the program to work. After dealing with complier differences I started to understand the processes involved. It contained a parser to generate Boolean equations, a Quine–McCluskey reduction engine and a fitter to create the final JEDEC fuse map. After gaining confidence I set about adding two additional features. First a mechanism to incorporate the macrocells present in the newer CPLD devices, and secondly (with my programming knowledge of the devices) extend the mapper to support the JEDEC files for all the CPLD devices I wanted to use.

This was a success, not only for my project but for my experience and understanding of CPLD features.

I now work with FPGAs regularly, and of course use 'C' or its more modern derivatives all the time. PLPL of course became a passing phase - but was along the way to structured aproaches such as Altera's AHDL, VHDL and Verilog.

I still have to find ways of engineering my way through budget limitations on equipment or tools; but this period was certainly an experience I am eternally grateful for.

So please don't forget PLPL in this history, as I won't forget how AMD, a large American corporation went a little further to help an enthusiastic abeit somewhat impoverished student further his career in the UK.

traneus
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RS flipflop using single PAL output
traneus   8/23/2016 8:51:18 PM
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I recall there was a way to build an RS (set-reset, no clock) flipflop using just one unregistered PAL output, using the hand-design approach. In CUPL, it was impossible, as CUPL would optimize out the redundant-to-CUPL product term.

antedeluvian
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re: How It Was: Programmable Logic
antedeluvian   12/9/2011 6:41:28 PM
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Here is a story in a similar vein. http://www.edn.com/article/509249-An_old_PAL_saves_the_day.php I have cross posted back to here

Max The Magnificent
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re: How It Was: Programmable Logic
Max The Magnificent   11/14/2011 6:50:25 PM
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Aubrey sent the pics to me and I just added them into the article...

antedeluvian
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re: How It Was: Programmable Logic
antedeluvian   11/13/2011 3:29:38 PM
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Accessing the "before" was difficult in a basement full of furniture from migrating children. Max has the photos now. I am sure the photos will raise a smile.

David Ashton
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re: How It Was: Programmable Logic
David Ashton   11/12/2011 10:02:53 PM
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Thnaks Aubrey for that insight. I still have a handful of these devices (PALCE22V10 and the like) recovered from old boards and have wondered what I can use them for (maybe hexadecimal 7-seg or 5x7 dipsplay decoders or something, but I am glad there is PALASM and PCs around to do it instead of working it all out manually like you did... PS. No before and after pics??

Max The Magnificent
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re: How It Was: Programmable Logic
Max The Magnificent   11/11/2011 3:34:31 PM
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The thanks should go to Aubrey for taking the time to write all of this down... ...maybe you have some tales to tell of your own?

ReneCardenas
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re: How It Was: Programmable Logic
ReneCardenas   11/11/2011 3:27:30 PM
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Max, thanks for the memory refresh, PAL and GALS were my intro to replacing LSI in NASA JSC costumized hardware.

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