Design Con 2015
Breaking News
Programmable Logic DesignLine Blog

Altera announces industry’s first OpenCL program for FPGAs

Clive Maxfield
11/15/2011 08:40 PM EST

 3 comments   post a comment
View Comments: Newest First | Oldest First | Threaded View
User Rank
re: Altera announces industry’s first OpenCL program for FPGAs
StefanMohl   12/9/2011 7:58:58 PM
FPGAs are actually very much better than standard CPUs for low-latency access and memory bandwidth. The main reason is that FPGAs have large numbers of internal parallel memory banks that can be manually controlled. CPUs only have automatically controlled caches in sequential "waterfall" levels. On a CPU, you are usually forced to read a cache-line of contiguous data from memory at a time, and hope that the algorithm access pattern fits the associativeness of the cache you happen to have. With FPGAs, you can stage your data manually and with high precision into thousands of simultaneously accessible memory regions, giving you literally multi-terabyte-per-second (not giga, tera!) bandwidth to your data. Also, you are not limited to reading bursts of a cache-line in size, rather you can read as much as you really need. Often, FPGA-cards also have several attached SRAM memory banks for fast-access off-chip storage, again improving on the von Neumann bottleneck. The key point in all this are the words "large numbers of, several, thousands of, simultaneously accessible", and so on. The whole point is that the FPGA is originally parallel, in contrast to CPUs that are originally sequential. That means that everything about the FPGA is based on parallel and multiple access (along with full manual control of data staging), and that really helps _a_lot_ when having tricky memory access problems!

User Rank
re: Altera announces industry’s first OpenCL program for FPGAs
DrFPGA   12/8/2011 11:49:11 PM
Double precision floating point efficiency will turn out to be the big issue. This is what most HPC folks are looking for and it is not that efficient in FPGAs. (Maybe Altera has or will publish some benchmarks to provide some evidence to the contrary?) If DP computation is improved then the issue is getting data on and off chip efficiently (from high speed memory)for things like sparse matrix computations. If someone can show a real world example that addresses these issues then I can be convinced. Otherwise it's just marketing fluff (IMHO).

Max The Magnificent
User Rank
re: Altera announces industry’s first OpenCL program for FPGAs
Max The Magnificent   11/15/2011 8:54:13 PM
One thing that makes this announcement particularly interesting is Altera's Fused Datapath technology which lets them implement single-and double-precision floating-point operations very efficiently...

EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
Top Comments of the Week
Like Us on Facebook Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll