I just received an email from a reader asking a rather interesting question...
I just received an email from a reader asking a rather interesting question. His message read as follows:
Greetings Mr Maxfield. I have been enjoying your PLDL Newsletter. The personal touches of your blog-like commentary approach are a refreshing touch compared to the multitudes of letters that others tend to publish!
I have a question for you... As a reviewer of books and since you have the art of the casual response and expertise in the logic device arena, you are likely to be the perfect person to answer this question. After being exposed to logic devices for about 20 years, I still consider myself a newbie to programming logic devices as I have been around since the before FPGAs and have to keep myself current with newer technologies. I have been studying Verilog and using it in combination with schematics for my logic designs, most of which fit into the small to medium size FPGA devices. I can't seem to find a good book that gives suggestions about how to structure an FPGA project.
I have seen the end results of some other engineers in their logic projects and they range from a simple schematic logic design to a fairly complex text-only design that is based upon some sort of table of contents located in the main project file.
The people that have used the schematics tend to make what could be very large multi-page schematic designs. The people that use the Verilog text-only design seem to refer to a table of contents which could be rather involved, even if the project is a small FPGA or CPLD device.
Would you be able to recommend a book or other resource that would point me in a good direction for understanding how to create and format the structure of logic-based designs? My knowledge of the structure of projects is a result of learning how to use systems like Quartus (Altera), ISE Design Suite (Xilinx) and Diamond Suite (Lattice).
Please feel free to publish my question as I would expect that there are other experienced-beginners like me that could benefit from your answer. If you do publish, please E-mail me a response anyway and you need not publish my name.
This is an interesting question, because it reflects the way in which a lot of people think when their roots are in a schematic-based, pre-language-driven-design (LDD) world.
I really wish I was standing in front of a whiteboard right now. As this reader says, some people tend to visualize things purely in terms of schematics – others are happier to capture their designs purely in a hardware description language (HDL) like Verilog or VHDL. And then there are folks like myself, who tend to think of things as a hybrid of the two.
Again, I’m imagining myself standing in front of a whiteboard and I’m specifically thinking about how I would describe things to the reader who sent in this question. Let’s assume that we are creating an FPGA design that comprises 10 functional blocks. If we wished, we could capture the top level of the design as a block-level schematic as illustrated below:
Now, someone who comes from a purely schematic-based design background would be happy with the idea of “pushing” into each of these blocks and capturing their contents as lower-level schematics.
By comparison, someone who is familiar with language-based design would be happy with the concept of “pushing” into each of these blocks and capturing their contents using Verilog or VHDL (remember that we’re assuming a purely digital FPGA design here).
If we were to look at the textural HDL equivalent of our top level schematic – which we could automatically generate from the schematic capture system and which would then be presented in the form of the main HDL project file – we would see a list of calls to our ten functional blocks along with the connections (wires / interconnect) linking them together. This is what the reader describes as “…a text-only design that is based upon some sort of table of contents located in the main project file…”
The ”table of contents” is actually the calls to the functional blocks.
A lot of people prefer this hybrid approach, whereby the top level of the design is captured graphically as functional blocks and the connections between them, while the contents of the functional blocks are captured in HDL (or as lower-level block-level schematics whose contents are subsequently populated using HDL).
Having said this, a lot of today’s digital logic designers are quite happy to simply capture everything in HDL. The point is that – irrespective of which way you do it – the highest level of the design is essentially a “Contents List” of the functional blocks forming the design. The way in which this “Contents List” is captures and/or presented – graphically or textually – is largely immaterial; they are simply different views of the same thing.
With regard to the question as to "Which is a good book that gives suggestions about how to structure an FPGA project”
… hmmm, that’s a tricky one. For this particular reader I think that the hybrid technique of capturing a top-level block-level schematic and then populating the blocks with Verilog is the optimal approach… but which is the best book for this… any suggestions?
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