The folks from Xilinx have formally announced their participation at DesignCon 2012 (“Where Chipheads Connect”) in Santa Clara, from January 30 – Feburary 2, at the Santa Clara Convention Center, Booth #732.
Xilinx Corporate Vice President, FPGA Development and Silicon Technology, Liam Madden, will jumpstart Xilinx’s activities by discussing the benefits and drawbacks of 3D IC standards in the Why Do We Need 3D Design Standards? panel. Xilinx industry experts will also present papers on Stacked Silicon Interposer technology and the design benefits of using the Zynq-7000 Extensible Processing Platform (EPP).
Throughout the week, Xilinx will demonstrate the latest Xilinx FPGA platforms featuring advanced Digital Signal Processing (DSP) performance, low power, FMC migration, high-speed connectivity, and Xilinx’s Agile Mixed Signal (AMS) Analog-to-Digital Converter (ADC).
What: DesignCon 2012
Where: Santa Clara, CA, Santa Clara Convention Center, Booth #732
When: Conference & Exhibits – January 30 – February 2, 2012
Tuesday, January 31
3:45 p.m. – 5:00 p.m., Ballroom E
Why Do We Need 3D Design Standards?
In this panel, Madden will explore whether the design community needs 3D-IC standards to accelerate the adoption of 3D design, and if so, how the standards can be implemented, the priority of these required standards, the challenges of applying these standards and how to get started. Panel participants will also provide their insights on how the many different industry groups are working together to prevent overlapping efforts or missing critical areas.
Wednesday, February 1
9:20 a.m. – 10:00 a.m., Great America J
Low cost/ultra high density and high performance wirebond package design and SI/PI analysis for FPGA with embedded dual core ARM CPU and dedicated DDR3 memory channel
During this presentation, Xilinx Senior Staff Signal Integrity Engineer, Namhoon Kim, will explore how the Xilinx Zynq-7000 EPP redefines the possibilities for embedded systems and how it gives system/software architects and developers a flexible platform to launch their new solutions. A detailed understanding and accurate modeling for estimating the worst-case noise both on physical layout and system levels is essential. Kim will introduce a full system-level simulation methodology to verify timing margin and voltage margin.
Wednesday, February 1
2:50 p.m. – 3:30 p.m., Ballroom C
Full System Channel Co-Optimization for 28GB/S Serdes FPGA Applications with Stacked Silicon Interposer Technology
Kim will also present a paper on Stacked Silicon interposer technology, the technology requirements and manufacturing processes to support 28GB/S Serdes application, and the package/PCB design metholodology for high speed systems.
Tuesday-Wednesday, January 31 – February 1
Kintex-7 FPGA-based reference design demonstrations
Using Kintex-7 325T FPGAs, Xilinx will demonstrate Kintex-7 FPGA-based reference designs featuring AMS, high-speed analog interface with DUC/DDC, and dynamic and static power reduction. The demonstrations will enable the use of real world analog data without requiring expensive test equipment, optimize system performance in both the analog and digital domains, and reduce power consumption.
Wednesday, February 1
2:00 p.m. – 4:00 p.m., Ballroom H
CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications
In this interactive workshop, Xilinx Distinguished Engineer, Simon Burke, and others will examine the various modeling and simulation challenges in 3D-IC design. Methodologies for the analysis of power delivery network, chip-to-chip communication, and thermal integrity will be covered using real case studies in designs.
About DesignCon 2012
DesignCon is the largest meeting of board designers, and the only event to address chip design engineers’ chip/system/package challenges. For more information, visit DesignCon.com.
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