I just heard that my good friend Brian Bailey will be the lecturer presenting a series of webinars next week.
These webinars will take place each day Monday through Friday. Each webinar lasts ~1 hour and includes a live question-and-answer session. But dont worry if you miss a day, because you can always catch up by viewing the archived version later.
Brian is my "go-to" guy whenever I have any questions with regard to EDA in general and verification in particular. He's written numerous books on test and simulation and ESL and verification and
In fact, Brian gave a lecture on SCAN technology in the UK that I attended more than a quarter of a century ago (it seems so weird saying that)
I still have the notes!
Anyway, here's the official announcement:
Kick-start your learning with our next Track: An Introduction to Functional Verification. Each day 25 attendees will receive a $5 Starbucks Gift Card.
An Introduction to Functional Verification (Register Now)
Monday, April 1 - Friday, April 5
11 am PST / 2 pm EST
This Track will introduce you to Functional Verification and will cover topics such as Fundamental Concepts, Models & Model Execution, SystemVerilog, and Universal Verification Methodology. It is intended to provide the basic Functional Verification concepts to prepare you for the next level of design.
The Track features lecturer Brian Bailey, a renowned expert working in the fields of Electronic System Level (ESL) methodologies and Functional Verification. He is currently the editor for EETimes' EDA DesignLine and also a contributing editor to EDN. Brian graduated from Brunel University in England with a first class honours degree in electrical and electronic engineering.
- April 1 | Day 1 - Fundamental Concepts (Sign Up)
- April 2 | Day 2 - Models & Model Execution (Sign Up)
- April 3 | Day 3 - Verification Methodologies (Sign Up)
- April 4 | Day 4 - SystemVerilog (Sign Up)
- April 5 | Day 5 - Universal Verification Methodology (UVM) (Sign Up)
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