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System Hyper Pipelining = 16 MCU cores on a Spartan-6 LX9 FPGA

Clive Maxfield
12/20/2012 05:39 PM EST

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Tobias Strauch, EDAptix
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re: System Hyper Pipelining = 16 MCU cores on a Spartan-6 LX9 FPGA
Tobias Strauch, EDAptix   1/8/2013 10:01:24 AM
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@modal, right, it is a kind of resource sharing. But SHP works on a standard FPGA, so the trick is the resource sharing on RTL.

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