Embedded Systems Conference
Breaking News
Programmable Logic DesignLine Blog

System Hyper Pipelining = 16 MCU cores on a Spartan-6 LX9 FPGA

Clive Maxfield
12/20/2012 05:39 PM EST

 11 comments   post a comment
NO RATINGS
View Comments: Oldest First | Newest First | Threaded View
<<   <   Page 2 / 2
Tobias Strauch, EDAptix
User Rank
Author
re: System Hyper Pipelining = 16 MCU cores on a Spartan-6 LX9 FPGA
Tobias Strauch, EDAptix   1/8/2013 10:01:24 AM
NO RATINGS
@modal, right, it is a kind of resource sharing. But SHP works on a standard FPGA, so the trick is the resource sharing on RTL.

<<   <   Page 2 / 2
March 2015 Cartoon Caption Contest: Mountain Climbing
March 2015 Cartoon Caption Contest: Mountain Climbing
The mountain had formed millions of years before when two tektronix plates collided.
208 comments
Flash Poll
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Top Comments of the Week