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Power Tip 40: Common-mode currents and EMI in non-isolated power supplies

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ed wozniak
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re: Power Tip 40: Common-mode currents and EMI in non-isolated power supplies
ed wozniak   1/27/2012 12:46:49 PM
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Can anyone explain how the circuit in Figure 2 is derived from the circuit in Figure 1? Figure 1 shows one side of C_STRAY1 connected directly to chassis. In Figure 2 neither side of C_STRAY1 is connected to chassis.

allananthony
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re: Power Tip 40: Common-mode currents and EMI in non-isolated power supplies
allananthony   10/20/2011 2:48:08 PM
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Perhaps the margin isn't there in such a market. After all, TI is a business that needs to maintain or grow their margin. Besides, you can control edge rates with simple circuits.

rbolanos
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re: Power Tip 40: Common-mode currents and EMI in non-isolated power supplies
rbolanos   10/19/2011 2:10:17 PM
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The edge of a fast switching FET can be controlled by putting a resistor in the gate. I would rather be able to control the rising edge than have it controlled by the chip. Best Regards

sharps_eng
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re: Power Tip 40: Common-mode currents and EMI in non-isolated power supplies
sharps_eng   10/16/2011 8:00:17 PM
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Can your colleagues at TI explain why they aren't offering edge-rate controlled FET switches, so that the emissions are minimised in the first place? Could it be that the silicon cost would rise because of the increased complexity and dissipation? I am always appalled at the half-baked circuitry that is released in silicon form, pushing this kind of unhygienic EMI behaviour onto the poor old customer's engineer who can do little except try and contain the beast. There are techniques to reduce emissions (e.g. balanced symmetric drive to cancel fields - you read it here first) that are as old as the hills but make no economic sense unless integrated into the chips. It is a question of understanding how a more expensive chip can make a cheaper product that gets to market sooner. That way lies quiet efficient products and happy customers' customers.

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