Some low-noise applications may require the power supply output ripple voltage to be less than 0.1 percent of the output voltage. This low ripple requirement easily can translate into filter attenuations significantly greater than 60 dB, which cannot be practically met with a single stage. In Power Tip 54, we discussed the design and time domain simulation of such filters. In this Power Tip, we discuss using P-Spice in closing the feedback loop around such a filter.
The trick to getting a low noise output is to employ a two-section filter. However, with the additional components in the filter comes additional phase shift, which can wreak havoc with a power supply control loop. In Power Tip 54, we discussed a strategy to minimize this phase-shift by damping the power supply filter and by putting most of the power supply’s capacitance at the output of the two-section filter. In this Power Tip, we further minimize the phase-shift in our control loop by employing peak current-mode control. This allows us to close the feedback loop at a high frequency with adequate phase margin with the two-section filter.
Figure 1 shows the P-SPICE simulation model of the power supply example we are about to consider. This model is based on the TPS54620, a step-down integrated FET, synchronous buck converter that comprises four sub-circuits: power stage and filter, error amplifier, modulator delay, and output divider. The power stage portion of the model takes advantage of the current-mode control of the controller IC. Current-mode control transforms the output inductor into a voltage controlled current source (VCCS) (G4 in Figure 1), feeding the remainder of the output filter and load resistor.
Figure 1: Current-mode control reduces system order by one
Click on image to enlarge
This transformation effectively reduces the system order by one and also eliminates a complex pole pair that is problematic in compensation design. From the power supply output (Node RLoad:2), the output divider takes a sample of the output voltage, which is compared to the reference voltage (Vref) by the error amplifier (G2). We will see later that capacitor C13 in the divider introduces a zero-pole pair into the control loop to help improve phase margin. The amplifier is treated as a second VCCS (G2), feeding the internal and external compensation components. The output is buffered by voltage-controlled voltage source (E2) and applied to transmission line T1, which simulates the power stage modulator delay (See Power Tip 53