Figure 2 shows the first simulation we need to examine and plan compensation of the power supply. It shows the voltage gain and phase from the error amplifier output node (C7:2) to the first node (L2:1) and second output filter node (RLoad:2). Here we have the choice of where to establish the regulation point of the power supply. In this example, we try to close the loop at 100 KHz. We can close the loop at the first section and only have 90 degrees of phase-shift to compensate, but we cannot compensate for output variations due to resistances in the second-stage inductor or dynamics of the second-stage filter. If we choose to close around the second stage, we need to compensate for an additional 90 degrees of lag from the well damped second stage, along with an additional 30 dB of gain. However, this approach significantly improves the power supply’s static and dynamic regulator.
Figure 2: The second filter stage adds 90o phase lag and reduces gain 30 dB. Click on image to enlarge
Figure 3 provides the gain and phase responses from node VAC to the error amplifier output divider/compensator (C7:2), and overall loop (RLoad:2). In the divider/compensator a type-three amplifier is used to provide phase-boost for 180 degrees of phase-shift near 100 kHz in the modulator/power stage portion of the loop. This type-three response is facilitated by the fact that the output voltage is large compared to the reference voltage, which forces a large divider ratio. With this large divider ratio, a pole/zero pair can be created with C13. The maximum phase-boost of the pair occurs at the geometric mean of the two frequencies. Since the geometric mean ratio of the two is near the divider ratio, the zero can be simply calculated as the maximum boost frequency (or crossover), multiplied by the square root of the divider ratio. The second zero in the compensator is set by the integrator capacitor C3 and resistor R3. The final consideration is to include the effects of the bandwidth limit of the error amplifier, which in this case is established by Reramp and C7. The overall loop bandwidth is near 100 kHz with 45 degrees of phase margin. This is accomplished despite the potential 360 degrees phase-shift of a two-section filter, as well as additional phase-shift due to modulator phase. Key reasons for the wide bandwidth include use of current-mode control, damping the second filter section, and use of C13 in the output divider to add an additional zero into the control loop.
Figure 3: Current-mode control, damping and divider zero facilitate near 100 kHz crossover.
Click on image to enlarge
To summarize, P-SPICE helps us to synthesize and analyze the control loop of a power supply with a two-stage filter. We were able to predict the impact of using current-mode control, damping a two-section filter, and adding an additional zero in the control loop from divider resistors. We also were able to synthesize a near 100 kHz bandwidth despite the potential 360 degrees phase shift from the filter.
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