If you want to start a heated discussion between a group of power supply engineers, all you need to do is ask them how they layout the grounds in a power supply. You will quickly learn there are two basic strategies. Each side will swear that the other approach has no chance of functioning as they smugly remember how well their last design worked.
The first approach is based on the concept of a single-point ground or star system (Figure 1). This idea steers the currents to control noise due to high di/dt in the conductors. A single-point ground is established at the ground of the control IC and all currents in the ground connection flow into that point. In this manner, high frequency, high slew-rate currents are not allowed to flow in sensitive paths such as the IC bypass capacitor, timing or analog circuit connections. Unfortunately, this approach can significantly degrade circuit performance due to increased inductances that result from the longer connections. For instance, in Figure 1, the star ground adds inductance to the transistor's source connection. The transistor's switching speed is related to this source inductance. As the transistor tries to turn off, the di/dt increases the source voltage and, hence, reduces the drive voltage gate-to-source. This slows the switching speed, which reduces efficiency. The additional inductance also distorts the current sense voltage, which can cause false tripping with peak current-mode control due to the leading edge spike.
Figure 1: Basic single-point grounding strategy puts significant inductance in source connection. Click on image to enlarge.
Probabaly the reason why heated debates emerge is because no one pat rule ever seems to work across the board (ha ha, what a pun).
I agree with the comment that a ground plane amounts to a large area single-point ground.
Thing is, whether on a single card, or in a large system of components, I guess the one basic goal is to minimize ground currents. And the knee-jerk reaction of isolating grounds doesn't always work, to this end, because then your risk frying components when their zero volt references drift too far apart.
One good solution is fiber optics.
Much depends on the power output level of the switcher. The simplified drawing in the article shows the typical single phase SMPS chip with on-chip gate driver. With literally dozens of chips to choose from this approach reaches its practical limit around 150W. For these middle-to-lower wattage supplies a single ground consisting of a compact star ("single point") topology is adequate, but a ground plane is preferred for best EMI performance. Much above the 150W (or so) level a separate gate driver device will greatly help decouple switching transients from the SMPS chip - this is where a two-mesh power and signal ground approach is necessary. In these designs the signal ground will host the SMPS chip and associated bias and feedback scaling/filtering circuits. These larger designs also tend to be poly-phase so a separate power ground is especially important to keep the multiple high current paths away from the control circuitry. The power ground is common to the gate driver, current sense, input capacitor(s) and OVP. Of course in isolated designs like flybacks there's almost always a third isolated "ground" on the output.
both are a single point star ground, one is just more distributed than the other :-)
and then you have , vias and components on both sides of the board,
all good fun.
My mark one eye ball rule of thumb is like yours.
Look at the currents, keep di/dt low.
and break every other rule at some point or other
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.