You can destroy a well-designed power supply with a sloppy layout. There are high power switching circuits as well as sensitive analog circuitry in a power supply, and mixing the two can result in chaotic operation. It even may appear that the power supply is oscillating as the control loop tries to correct for the unintentionally injected noise. A few minutes of planning and reviewing your layout can save days of lab check-out and debugging as you sort out noise issues.
Figure 1 shows a layout where the engineer did not do a good job of isolating the switching and noise sensitive circuits. In this case, he inadvertently capacitively coupled the switching node of a buck regulator into the input of the error amplifier. This often happens because of the large number of components connected to the error amplifier. With this controller IC, it is even more likely to be a potential problem since the switch node is two pins away from the error amplifier input. Fixing this problem is relatively easy. Simply separate the nodes and then run a ground connection between the two to serve as a shield. It seems the IC designer realized this potential problem by the inclusion of a ground pin between the switch node and error amp input.
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Figure 1: Watch noise sources (switch node) and high impedance nodes (amp input).
presents a case where the designer did not think about current flow in bypass capacitors and snubber resistors, and ended with high-frequency noise in his power supply output. This is a synchronous buck regulator which has a snubber (C1 and R2) to provide noise reduction. In synchronous buck regulators, there are two switching transitions. The first occurs when the high-side switch turns off, the output inductor drives the switch node to ground, and the low-side switch turns on. This is a benign transition as the switches turn on and off with zero voltage across them. For the other transition, the low-side switch turns off and current continues in its body diode until the high-side switch recovers it. A surge of current is generated, which excites the resonance of the package inductance and the capacitance associated with the switch node. If the switching dead times are short enough, the diode can be prevented from conducting, but shoot-through can result in a similar surge of current. This is not a benign transition. The recovery of the diode and capacitance on this node is hard switched, and the ringing voltage on the switch node can substantially exceed the input voltage. This ringing will have components in the 100 MHz range, which can couple to the output through the distributed capacitance of the output inductor (L1). The snubber damps the resonance, so it carries high-frequency current.
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Figure 2: Minimize ground plane current for reduced noise problems.
The person responsible for layout could have improved his noise situation with proper component placement. First, the chip bypass capacitor could have been better placed to keep high current (shown in light blue) out of the board. It works better if the bypass capacitor is located horizontally below the IC. This facilitates short connections to both power and ground, minimizing inductance and keeping high frequency currents out of the ground plane. Secondly, there is significant inductance in the snubber hook-up, which also results in high-frequency current in the ground plane. Snubber components could be placed along the bottom of the IC, to the right of the relocated bypass capacitor. Finally, this layout is another example of mixing switching and sensitive circuits. The connection to the snubber is located adjacent to the high-impedance voltage sensing circuit.
To summarize, thoughtful placement of power supply components save checkout time on your prototypes. It is important to recognize that there are both noise-sensitive and noise-emitting nodes in your design. You will want to keep them separate. Also, pay attention to bypass capacitors and snubbers. Keep their leads short and keep high frequency/high AC currents out of ground planes with proper component placement. Finally, preserve your ground plane integrity by minimizing the amount of other etch runs on these layers.
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