Testing low-voltage, high-current power supplies is quite a challenge, due to inductance and active load capabilities. The two main challenges are minimizing load inductance in the test setup and to taking a proper voltage measurement.
High-performance processors demand subvolt power rails that can rapidly source and sink current. It is a testing challenge to duplicate these large current swings to verify power supply performance. The two main challenges are to minimize the load inductance in the test setup and to make the proper voltage measurement.
Inductance in your test setup is a problem, but when combined with low voltage and rapid current transients, it is a killer. Between the load and the inductance, you have a simple L-R circuit that limits di/dt.
For example, your processor may have a 1-V supply with a 10-A load, which could simply be modeled as a 1V/10A = 0.1-Ω resistor. If you hooked up that resistor with three inches of wire, you would add about 50 nH of series inductance. The time constant of that circuit is L/R or T = 500 ns. The expression for the current takes the following form. (The maximum rise occurs at zero and has diminished by 63 percent at one time constant.)
The maximum rise time for a 10-A current step would simply be I/T or 20 A/µs. This is a much smaller rise time than the 100 A/µs the processor guys throw around, and it highlights the need to minimize inductance.
Obviously, wirewound and physically long resistors do not make good test loads, due to their self-inductance. A good rule of thumb to estimate single-wire stray inductance is 15 nH per inch. One effective way to reduce this hookup inductance is to use multiple SMT resistors in parallel over a ground plane. To minimize interconnect inductance, you should include these load resistors on the prototype power supply board.
The figure below shows an example load test circuit that includes the load resistors, series MOSFETs, and drive circuitry. This provides two options to drive the load switch MOSFETs: a buffered drive driven by either a pulse generator or an onboard timer.
An onboard transient load tester reduces interconnect inductance.
(Click here for a full-size version.)
The following image demonstrates the difficulties of generating high di/dt in a 1-V power supply and measuring the transient response. It shows the load current in green as it increases from 0 to 20 A in 2 µs for a di/dt of 10 A/µs.
This 50-A/µs rated load really has 2-µs rise times.
(Click here for a full-size version.)
This current waveform was generated with a load rated at 50 A/µs with virtually zero interconnect length. At first, there seemed to be a conflict, because the load was rated for 50 A/µs, but on inspection of the active load's datasheet, there was a 2-µs rise time specified with 100-A current capacity. At less than 100 A, di/dt was reduced proportionally.
The figure also shows the envelope of the transient response in yellow. Interestingly, there are three distinct ripple regions. The first is during the no-load operation, where the buck inductance is the greatest. The second is during the transient, where the power stage goes toward full duty cycle, reducing the buck inductor ripple current. The third is during the high-current output, where the inductor value has diminished due to current, and the high-frequency spikes are the highest.
There are also current injectors available that feature very fast transients that can give you insight into system resonances and stability. However, they tend to have limited current capacity. The figure below shows an example.
A current injector can create a near vertical 50-mA current step.
The top scope shot shows the power supply response in black to a red current step created by a low-performance active load. The power supply shows almost no response as the control loop crosses at a high frequency and corrects out any regulation error caused by the current step.
The bottom traces were created with a current injector featuring very fast transitions. The red current trace is nearly vertical and generates a damped sinusoidal response from the power supply. This could be indicative of low phase margin in the control loop or inductance in series with output capacitors. However, these traces were generated with only a 50-mA current step and can show only small-signal responses. These current steps are nowhere near the 100-A/µs range a processor may require, and they cannot be used to measure the large-signal response.
To summarize, it is quite a challenge to test low-voltage, high-current power supplies properly, due to inductance and active load capabilities. In a 10-A power supply, 50 nH of inductance (three inches of interconnect) can limit di/dt to 20 A/µs, making rise times worse at higher currents. Test equipment that can generate fast-rise-time, high-current steps is lacking, because either the rise times are too slow or the current capacity is insufficient. It is generally best to include switchable load resistors as part of the prototype power supply for this type of testing.
Please join us for the next Power Tip, where we will look at the implication of envelope tracking on supplies.
Check out TI's PowerLab Notes for a designer's perspective on his power supply designs: PowerLab Notes: AC/DC phone and tablet chargers.
For more information about this and other power solutions, visit www.ti.com/power-ca and TI's Power House blog.