Some standards are very prominent in our industry, such as SystemVerilog, but verification methodologies rely on much more, including SCE-MI...
A few days ago Toshio Nakama, CEO of S2C wrote a blog titled Why SCE-MI has not been Widely Adopted Today? First of all, hands up if you know what SCE-MI is. Not a lot of hands up. OK, hands up if your company uses emulation or FPGA prototyping. Lot more hands up now. Well, you are probably a user of SCE-MI. It is the standard that defines how hardware assisted platforms talk to software - that a testbench, software simulator or virtual prototype.
In their blog Nakama states: S2C started to work on a SCE-MI on FPGA-based prototype project in 2006 with one of our partners in Japan. Before 2010, we did not see a large number of requests for SCE-MI. However, we are seeing an increase in demand for such transaction-level co-emulation solution in the past one year and have already engaged in a number of projects. The use of prototyping is on the increase and this will drive further adoption of this standard. So who defines the standard? Well, this is where it gets interesting.
The standards group has existed within Accellera since 2001, and it existed before that as a consortium of users and vendors. At that time it really was for emulation only. Over time the number of emulation companies dwindled as they consolidated and today we are really left with just three significant Mentor, Cadence and EVE. But at the same time, the use of FPGA prototyping has been accelerating. However, most of the companies involved with this are small. So the standard continues to be set by the emulator vendors. This has created problems. I chair this committee and have done so ever since it became an Accellera committee. We are down to three active members 2 of the emulator vendors and 1 customer. How can we make decisions for the entire industry? It is getting to be difficult, especially when we cannot converge on a solution.
So, I am asking everyone out there who makes an emulator, FPGA prototyping system, or uses these in the course of their design and verification to step up their participation. This will ensure that this standard continues to evolve and to deal with the growing demands being placed on it by new types of application.
This standard may not get the visibility of the language standards such as SystemVerilog, but it is still an important part of a complete verification solution. Without it, verification will cost you more, give you less model portability, and reduce the number of companies willing to write transactor models for hardware assisted verification.
Without increased participation, the standard will cease to evolve. Get involved now. Sign up on the Accellera site and join the ITC effort, attend our weekly meetings, or let me know how you want to participate in the evolution of this standard.
Brian Bailey keeping you covered
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