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If You Could Have the Ideal Programmable Logic Device, What Would it Be?

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realjjj
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old news but ....
realjjj   6/27/2016 5:40:26 PM
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Deep learning is one. Our computers are not well suited for that and all key segments will require it, from glasses and robots to IoT and server.

Max The Magnificent
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Re: old news but ....
Max The Magnificent   6/27/2016 6:08:23 PM
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@realjjj: Deep learning is one. Our computers are not well suited for that and all key segments will require it, from glasses and robots to IoT and server.

That's a good one -- as little as 3 to 4 years ago deep learning seemed to be of achademic interrest only -- now just a few years later it's not just dipping its toes in the mainstream -- it's plunged right it and it's appearing everywhere -- it's like "A technology for all seasons" type thing

betajet
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If and only if
betajet   6/27/2016 7:23:53 PM
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I was around when FPGAs first hit the market.  At that time they were slow and expensive and thus not very compelling as a product.  The Xilinx 4000 series was much more interesting, but again very expensive.  The first family that was really exciting to me was the Xilinx Spartan series, especially the Spartan-II and Spartan-IIE.  Those were very nice chips: clean architecture, quite fast, and reasonably cheap.

Around 1990 I thought FPGAs were a very promising technology and could be extremely successful if and only if the vendors published the internal architecture so that anybody could write tools for them.  The fact that they didn't is IMO why ARM processors are so dirt cheap and ubiquitous while FPGAs remain a "boutique" technology.

These days my favorite architecture is Lattice iCE40 because Project IceStorm reverse-engineered the internals and you can get open-source tools.

seantellis
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Ideal features
seantellis   6/28/2016 12:57:07 AM
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I'm mainly a hobbyist, so in that context, I would want something that behaved like a modern microcontroller:
  • Standardised interface and bitfile format for programming
  • Wide range of sizes with the same architecture
  • Smallest sizes hobbyist-friendly (i.e. DIP packages)
  • Open source tools
  • Nonvolatile memory on-board for configuration data
  • Onboard clock module
  • Integrated CPU (ARM based, naturally)
  • Single supply

Basically, something as easy to get started with as possible - hook up a USB data connection and a 3.3v supply, and off we go.

DigitalEngineer
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Re: Ideal features
DigitalEngineer   6/28/2016 7:37:35 AM
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Good points, I'll drink to that.

Wonder why it hasn't been done yet.

I would also like to add more on-FPGA memory (e.g. SDRAM on additional dies) for the CPUs and user logic (e.g. shared).

Max The Magnificent
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Re: Ideal features
Max The Magnificent   6/28/2016 8:55:54 AM
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@DigitalEngineer: Good points, I'll drink to that.

Make mine a double :-)

antedeluvian
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FPGAs
antedeluvian   6/28/2016 9:34:39 AM
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Max

 Were you around when the first FPGAs appeared on the market? If so, what did you think about them at that time? Did you have any idea how far they would evolve?

I was around before FPGAs as you may remember from my blog "How It Was: Programmable Logic". One of the reasons I never went down that path was the relatively high current consumption. Their capabilities also outgrew my needs very rapidly and so I was left stuck in the mud of microcomputers.

Max The Magnificent
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Re: FPGAs
Max The Magnificent   6/28/2016 9:36:25 AM
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@antedeluvian: ...I was left stuck in the mud of microcomputers...

It's easy to knock them, but microcontrollers (especially today's offerings) really are rather amazing -- try imagining a world without them :-)

antedeluvian
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Re: FPGAs
antedeluvian   6/28/2016 9:39:24 AM
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Max

try imagining a world without them :-)

Given my history- that would be like I was never in this world. Maybe I would have been a shoe salesman.

Clive
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Re: FPGAs
Clive"Max"Maxfield   6/28/2016 9:46:59 AM
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@Antedeluvian: ...Maybe I would have been a shoe salesman...

And a darned fine one at that! :-)

antedeluvian
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Re: FPGAs
antedeluvian   6/28/2016 9:44:51 AM
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Max

but microcontrollers (especially today's offerings) really are rather amazing

I couldn't agree more. To support your assertion- Did you see my series of blogs about implementing a True RMS Measuremnt in hardware on a microcomputer (PSoC- an interesting variant of an FPGA)?. Part 1, 2, and 3

 

Clive
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Re: FPGAs
Clive"Max"Maxfield   6/28/2016 9:47:48 AM
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@Antedeluvian: ...Did you see my series of blogs about...

Of course I did :-)

MeasurementBlues
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Old EDN
MeasurementBlues   6/28/2016 7:34:54 PM
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You might be wondering why I even have these old EDN issues. It's becaase EDN tuned 60 years on May 8, 2016. Throughout the summer, we'll be posting articles about the past and the future of electrical engineering.


While at the electronics flea market in May, I ran across someone trying to sell old EDN issues. Turned out he had five boxes of them ranging from 1982 to 2000. While there are many missing issues, there's still plenty to work with. There are tons of articles about designing with digital logic, especially in the early days of these issues. EDN used to publish microprocessor directories.

Even the ads and product write-ups tell a story, you can see what products were new and when. I even found EDN's first coverage of Microsoft Windows in 1985. It's all of one paragraph buried in the product section way inthe bask of the issue. I've written a blog about it that will appear on EDN sometime in July or August.

 

traneus
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FPGAs and microprocessors
traneus   6/28/2016 8:18:42 PM
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I started designing embedded systems professionally in 1974, so I have lived the development of FPGAs and microprocessors. Since 1980, I have been designing multichannel VLF radio receivers, shifting from analog to digital implementations. My first digital implementation used 68-pin multiplier-accumulator chips.

In 1998, FPGAs did not yet have multipliers, so I had to use a 64-bit microcontroller. A colleague consulted the EDN Microprocessor Directory, and found two candidates: DEC Alpha and IDT 4650 MIPS microprocessors. The 4650 had a straightforward synchronous bus, so I used that. I had to use open-source development tools, because proprietary tools we bought would not permit assembly code on the bare metal. Using a large fast processor to run a single ten-microsecond loop was too far outside the proprietor's concept space.

In FPGA's, I require up-front knowledge of timing, even if these specs are more conservative than the chip is capable of. For me, timing is an integral part of the design process, not an afterthought. This is why I programmed that 4650 in assembly code on the bare metal: I could calculate conservative execution times before building hardware.

traneus
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Former professional vs hobbyist class distinction
traneus   6/28/2016 8:38:52 PM
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I am thankful that the former formal class distinction between professional and hobbyist, has disappeared.

In college, I started subscribing to Electronics at $30/year. I kept that subscription until Electronics's 1982 demise. I was not qualified to subscribe to EDN or Electronic Design until 1980, when I started work at a proper company.

fragro
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Micron Automata?
fragro   6/29/2016 7:35:02 AM
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Anybody any opinion on that one? Seems that it addresses things we do not have a grasp on, yet.

KarlS01
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A chip with writable LUTs and memory blocks.
KarlS01   6/29/2016 9:45:25 AM
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Forget about "gates" or worse yet "equivalent gates".  I want something to implement interface protocols for IO.  Then DSP and computational algorithms for processing.

Grouping LUTs with memory with both addressable and writable would greatly reduce synthesis and P&R to reconfig a chip.

There are usually only a small percentage of nets that limit clock speed and the rest can be done by programmable controllers.

The ability to create delays to deskew data on asynch interfaces would be nice, too.

Also forget about logic optimization mainly because little of the LUT functionality is actually used.  It is there so the LUT logic function can be customized so "gates" are not saved.

The LUT is a small RAM so it should be loadable for customization.  Other things included in the building blocks such as fast carry are also needed.

 

betajet
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Re: A chip with writable LUTs and memory blocks.
betajet   6/29/2016 11:27:07 AM
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KarlS01 wrote: The LUT is a small RAM so it should be loadable for customization.

You can already do this with some Xilinx Spartan parts.  In fact, Spartan-6 has a dynamically configurable 5-input LUT primitive called CFGLUT5.  For some Spartan parts (e.g., Spartan-3) the Xilinx software tells you where to find distributed RAM and ROM in the bitstream, which you can then overwrite to get a different function.  It's not well documented, but worth the effort if you need the capability.

KarlS01
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Re: A chip with writable LUTs and memory blocks.
KarlS01   6/29/2016 5:19:57 PM
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@betajet:  And they just announced a block ram designer.  I have a way to execute C statements using memory blocks and LUTs.  Three memory blocks and a couple of hundred LUTs is faster than a soft CPU and certainly small enough to preplace many on an FPGA then personalize the function by loading the RAMs with whatever function is needed.

The size and speed to load the bitstream is a bit of a concern, but OK to show feasability.  Still a lot to think through.  So far the resource usage of CPUs limits how many are practical on a chip and the CPU speed is slow compared to a hard CPU, but 2 hard cores is probably the limit.

Maybe just use one cluster to load all the memories from flash.

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