Recently, our sister company UBM TechInsights delivered a webinar on how it goes about doing the magic it does to uncover the secrets within semiconductors and other bits of integrated circuitry used in all the devices we’ve come to know and love.
For those not familiar with TechInsights, it’s the secret lab up in Canada where our colleagues rip open anything from cars (Chevy Volt), to refrigerators, TVs, phones, tablets, laptops, smart meters, and much more for your geek porn pleasure.
Each dismembered product is carefully analyzed by TechInsight’s engineering teams, who get to do amazingly cool things to them, like dissolving them in acid to figure out what materials they’re made of.
In fact, delayering semiconductor die is often useful for a plethora of applications - circuit reverse engineering, failure analysis, transistor characteristics measurement, circuit edit, and more.
Circuit extraction is likewise a good way to get valuable evidence of use in competing products that is difficult to find using other means – so it’s a patent lawyer’s best friend.
TechInsights’ delayering techniques involve a wide range of parameters which include effort, equipment, cost, risk and accuracy - so choosing the right process, tools, and techniques is vital.
It also, of course, requires sound knowledge of semiconductor architecture so as to be able to sketch circuit design schematics for you guys afterwards.
Indeed, TechInsights CircuitVision goes a step further and offers a highly interactive, easy to navigate view into circuit designs, as well as the physical implementation on the IC.
Hierarchical schematics demonstrate the design from the block down to gate level - all linked to the original layout, showing the extracted gates and associated interconnect.
Trust me, it’s neat. And not only is it neat, but for the first time ever, TechInsight’s is opening the kimono a bit with a webinar video overview of the delayering process as well as the tools and expertise it uses to discover how a processor was designed, formulated and built - after it was actually delivered to market.
You can see the presentation here. Warning there is some really heavy geek factor in here!
If you’re still not convinced, here’s a little taster of what you can expect from the video:
• Technical and IP reasons why delayering techniques are important - Technical - failure analysis, design verification, etc - IP - competitive intelligence, IP assertion
• An overview of the semiconductor process - Different constructions and materials determine complexity of delayering process
• An overview of available manual and automated delayering techniques - Pros and cons of each method must be considered to achieve desired and accurate effect
• Criteria and challenges in choosing the correct delayering technique - Costs, control, removal rates, difficult structures to maneuver, etc
• How to image the circuit results and trace signals during the delayering process - CircuitVision allows engineers to trace signals, and understand specific circuit elements and larger functional blocks on a chip
Chipworks( also from Canada ) has been a long established reverse - engineering company and always seesms to score first. Like they were the first to publish x-section of Intel finFET and showed the sloping side walls. Just last week they posted the first application of wide I/O memory in a consumer product ( Sony Vita ). And many more. Good Luck to Techinsights. The more the merrier. Let the games begin.
Oh, doesn't this bring me back memories! Part of my diploma project at uni was reverse engineering blocks of a video chip. I spent ours of etching and photographing, watching the chip doing its little striptease under the microscope. Then, putting it all together, into a circuit. Of course, back then it was mostly about look-up tables and sprites were the bee's knees. I think the minimum line width was 4-5um on the chip and I don't quite remember but I think it had one layer of metal and one layer of poly.
Back then, my "Electronic Devices" lecturer at uni was explaining to us how semiconductor physics would break down under about 1um. In any case, lithography would hit a brick wall, for sure! :-)
Now, with 11nm around the corner and talk about feature sizes down to 5nm, I think those worries were a bit premature!
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.