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alex_m1
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Re: Easic will solve
alex_m1   5/23/2015 3:46:08 PM
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Sorry , it's not eAsic, it's another company(monolithic 3d ), by the same founder - zvi orbach.

Detailst of tech:

http://www.monolithic3d.com/uploads/6/0/5/5/6055488/fpga_flyer.pdf

rick merritt
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Re: Doea anyone really want to discuss a new design?
rick merritt   5/23/2015 3:24:31 PM
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@Karl: If this is real, send me some materials that describe your work at a high level for review as a possible story.

rick merritt
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Re: Easic will solve
rick merritt   5/23/2015 3:22:34 PM
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@Alex: If eASIC has such hot technology I hope they outlined that in their S1...and I hope Wall Street understands it ;-)


They should also send me some background on it

KarlS01
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Doea anyone really want to discuss a new design?
KarlS01   5/23/2015 10:27:48 AM
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"Pradeep Sindhu, Juniper's co-founder and CTO, put out a call for a next-generation microprocessor architecture that has "the agility of a general-purpose CPU and the speed of a dedicated ASIC — that's a first-class problem that needs to be solved," he told the many microprocessor engineers in the audience."

After 30 years of experience in mainframes, mini-computers, and micros I have a scalable design consisting of 3 dual port memories, an ALU, comparator, some incrementers that executes source code taking one start cycle and one cycle per operator in assignments.
 

Execution speed is achieved by overlapped access of the memories and use of dual ports.

The present Stratix III design uses just over 200 LUTs and 3 embedded memories.  The execution model could be to DMA a thread and its data, execute, then return results.

It would resemble loading caches with control and data for the next thread while executing the current thread.  The small size allows for multiple implementations on  a single chip/FPGA, and the DMA streaming is memory efficient.

The pipe-lining and excessive memory accesses are replaced by an efficient dataflow.

alex_m1
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Easic will solve
alex_m1   5/22/2015 4:46:04 PM
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Rick, with regards to eAsic - outside of it's great tech , they have ideas on how to create FPGA with the density of an ASIC using 3DIC, and that might take us to "microprocessor architecture that has ,the agility of a general-purpose CPU and the speed of a dedicated ASIC" like one of the lectures talked about.

 

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