The time is ripe for a new direction to take advantage of the unique features of PCMs/RRAMs as single component pulse integrators with the non-volatility and plasticity that make them attractive as possible synapses and neurons in learning machines.
Controlling, on-to-off resistance ratios and heat transfer characteristics provides the means to control the threshold voltage and the time of the post-firing refractory period. The rate of VO2 film deposition (oxygen stoichiometry), the choice of substrate (SiO2 or Al2O3) and device dimensions were the key experimental and simulation variables.
A generally applicable electrical-thermal model for IMT based devices was developed and verified from electrical measurements of VO2 devices, which was then used it for designing IMT based artificial neurons.
The work culminated in the demonstration of an artificial neuron with integrate-and-fire and post firing refractory period characteristics capable of operating at 0.8 V. with simulations which predict with scaling further voltage reduction sub 0.3Volt operation will be possible.
Brain gates the way to go
Late last year at IEDM-2016 Toshiba with Hynix announced plans for a 4Gbit MRAM and even although perhaps 3 to 4 years away from a commercial and proven product, plus the progress made by other MRAM vendors must be read as danger signals for PCM/RRAM product developers. It may be time for the PCM and RRAM communities to look at brain-gates as a potentially more rewarding future direction where their technologies will be able to offer unique features. Brain-gate: a circuit or array where the unique features of PCM/RRAM are integrated with conventional silicon.
Read Part 1 here.
—The career of Ron Neale, as a researcher, process developer, and designer of solid-state memory devices, stretches back over 50 years. More recently he has been involved as a consultant, writer, and keen and critical observer of the latest memory developments. His EE Times Progress Reports on the state of play in memory developments have a large following. He has a number of firsts in memory device development and manufacture in the areas of phase change memory (PCM) and programmable read-only memory (PROM), including anti-fuzes and programmable VIAS. He holds 20 patents in the area of memory and programmable interconnect and is a member of The Institute of Physics and a Chartered Physicist.He is also qualified as both a mechanical and electronic engineer. As well as memory device development and research, Ron has also held senior positions in companies involved in computer development and the manufacture of semiconductor fabrication equipment, as well as serving a stint as editor of Electronic Engineering magazine.
[Ref 1] Demonstration of hybrid CMOS/RRAM neural
networks with spike time/rate-dependent plasticity, V. Milo1et al, PROC IEDM 2016.
[Ref 2] Low-Voltage Artificial Neuron using Feedback Engineered Insulator-to-Metal-Transition Devices J. Lin et al, Proc IEDM 2016.