TechInsights discusses the structural differences between Samsung's 32L and 48L 3D V-NAND.
Samsung has mass-produced their 48-layer (48L cell gates in a NAND string, named 3rd generation) 3D V-NAND chips for SSD (solid state drive) applications such as SSD T3 (mSATA and 850 EVO V2), NVMe SSD (PM971-NVMe) and enterprise SSD (PM1633a). In all devices, they have a number of 48L 3D V-NAND memory chips in which 16 NAND dice are stacked with wire bonding technology. Samsung integrated 512 GB memory cells in the 48L V-NAND chip, which means each NAND die has 32 GB (256 Gb). Samsung’s 32L (2nd generation) V-NAND die contains 10.67 GB (85.33 Gb). So, what are the differences between 2nd and 3rd generation V-NAND devices? Have they just increased the number of cell gates from 32 to 48?
TechInsights has completed detailed analysis of the two device types; looking from cell architecture, materials, layouts and package viewpoints.1 Here are some highlights of that analysis:
Memory density and die floor plan
Figure 1 shows 16 48L V-NAND dice with two F-Chips in an MCP (multichip package). Die efficiency is higher in the 48L. The 32L V-NAND die area is 84.3 mm2 while the 48L V-NAND die measures 99.8 mm2, which is a 17.3% increase due to greater die length (Figure 2). Memory density per unit die area is increased to 2.57 Gb/mm2. The memory density of leading-edge 2D planar NAND devices such as Toshiba 15 nm TLC NAND is 1.28 Gb/mm2, (see more on our analysis on the Toshiba 15 nm NAND). The key feature differences in die floor plans are 1) planar (NAND memory array) area, 2) bitline switch and page buffer area, 3) LOGIC and peripheral area, and 4) the addition of F-chip. Each die has two planes. The NAND memory array area increased from 48.9 mm2 to 68.7 mm2 which is 40.3% larger. The area of the bitline switch circuit is the same as that of the 32L, while the page buffer area is 20% smaller. The logic and peripheral circuit area is 34.8% reduced. In other words, Samsung dramatically shrank the area of the page buffer and peripheral region so that they can further increase memory density and die efficiency. Die thickness is also reduced from 132 μm to 36 μm for the sixteen die stacked in the MCP.
Figure 1. Samsung 48L V-NAND device stacked with sixteen vertically stacked NAND dice and two F-Chips, teardown image (Source: TechInsights)
Figure 2. Comparison die photograph with 32L and 48L V-NAND (Source: TechInsights)
F-Chip newly adopted
Samsung introduced the F-Chip embedded in the NAND flash MCP during the ISSCC2015 event last year. In general, the hardware architecture of SSDs is composed of memory controllers, NAND flash memory and DRAM.
The F-Chip realizes a point-to-point topology on I/O buses between memory controllers and the F-Chip suffering from undesired reflections at stubs in channels. In addition, the F-Chip reduces the capacitive loadings on the F-Chip-to-NAND interfaces by implementing and evenly distributing two internal I/O buses between the F-Chip and NAND devices. It supports a retiming mode to transfer I/O signals from the memory controllers to the NAND devices.
It also improves reduced timing margins due to inherent timing jitter that occurs in NAND devices with an asynchronous interface. A single F-Chip is connected with eight V-NAND dice, which means two F-Chips are embedded in a package with sixteen dice. Figure 3 shows the F-Chip die removed from the MCP. The F-Chip includes some circuit blocks such as ROM, DC generator, CMD decoder, data path, TX/RX and wire bonding pads. The F-Chip die area measures 0.057 mm2.
Figure 3. F-Chip die removed from Samsung 48L 3D V-NAND MCP (Source: TechInsights)