The recent push for finer-geometry semiconductor processes has resulted in a vast increase in the number of process options available.
The recent push for finer-geometry semiconductor processes has resulted in a vast increase in the number of process options available. Fine-tuning of these processes, so as to achieve an optimal speed vs. power trade-off, has yielded scores of process options at the 90-nanometer level.
In addition to selecting one of the many process generations in production (0.15 micron, 0.13 micron, 90 nm, for example), today's designers must be prepared to select the most appropriate process option for their particular design, and they must do so as early as possible in the design cycle. This decision matrix is further complicated by the varying availability of standard-cell libraries, memory and intellectual property (IP) for use with a specific process.
The basis for a solution to the process selection issue is emerging in the form of a Silicon Virtual Model (SVM). An SVM captures the electrical and physical characteristics of a specific process, creating a macro model suitable for evaluating speed, power, area and yield trade-offs. Too abstract for addressing detailed design issues such as critical-path evaluation, an SVM nevertheless offers useful guidance in determining the suitability of a process for a particular design.
For example, knowing the maximum number of gates between flip-flops for a design's target frequency will not guarantee design feasibility, but it may well eliminate a low-power process option as a possibility. The high degree of abstraction inherent in an SVM can provide insights that are otherwise obscured by the massive amount of data a typical design kit comprises.
Macro models of standard-cell libraries, memory and IP blocks are presented with an SVM for a process. Making library, memory and IP selection at an early stage in the design cycle greatly decreases the risk of design delays later in the cycle. Such delays often arise from a poor understanding of what IP is available for a specific process (option), or from uncertainty about whether the selected IP meets the design's high-level constraints.
Certain architectural decisions may also be considered at this point in the design cycle: Memory redundancy schemes may be selected to improve die yield; standard-cell libraries may be compared for speed and power; off-the-shelf IP may be considered as a pragmatic substitute for custom design. While these decisions may need fine-tuning as the design develops, the insight provided by an SVM minimizes the likelihood of costly revisions later in the design cycle.
Tools are being developed to leverage the usefulness of an SVM.
Moving beyond the limited capabilities of an Excel spreadsheet, such tools provide the ability to quickly navigate the process-plus-library-plus-IP matrix of choices and thus make well-informed technical and business decisions. These tools allow high-level design assembly, creating logical and physical views of the design before any register-transfer-level code is written.
Though these early views of a design are highly abstract, they provide a concrete basis for process, library and IP selection. By revisiting this high-level representation as the design progresses, designers may see the impact of detailed design implementation decisions in the context of the overall design long before all portions of the design have been implemented.
While the choice of a semiconductor process, library, memory and IP has become increasingly difficult, tools are emerging to ease the burden.
Bill Sommer is chief technology officer at Giga Scale Integration Corp. (Cupertino, Calif.).