Some industry observers believe strained silicon is preferable to silicon-on-insulator or strained SOI at 90-nanometer design rules, citing SOI, which often requires new design libraries, as being more difficult to integrate. Similarly, strained silicon is claimed to be easier to deploy as a substrate material for highly advanced ICs. In truth, whether strained silicon or strained SOI is used has little effect on the design side; the switch from bulk silicon to SOI has far greater impact.
The misperception of strained silicon's value vs. that of SOI arises, in part, from a misunderstanding of what each material brings to the table. Strained silicon is a solution for increasing, first, the transistor current and then the circuit switching speed, as the higher current enables more rapid charging and discharging of the interconnect and cell capacitances. Strained silicon does not, however, bring any solution to the scaling problem. Shrinking the transistor gate length reduces the threshold voltage, creating the short-channel effect. SOI controls that effect.
Partially depleted SOI transistors deliver a higher drive current thanks to the floating-body effect. The body is charged up under static biasing by physical-current components (impact ionization and gate-tunneling current) and also under dynamic biasing by capacitive coupling between the body and the other terminals. This charging serves to lower the threshold voltage, improving the drivability of the transistor.
Thin is in
With fully depleted devices, the short-channel effect is primarily controlled by the thickness of the silicon film the thinner the film, the better the control. Less than 20 nm of silicon should be used at the 90-nm node and less than 15 nm at the 65-nm node for planar single-gate, fully depleted transistors. The thickness constraint may be released if more complex fully depleted structures are used, such as double-gate, triple-gate and FinFET devices.
Strained silicon implemented on partially depleted SOI is known as strained SOI. With this material, the drive current is increased thanks to the lower threshold voltage and enhanced mobility. Getting the same off-current at a given temperature (fixed by the application) is always possible through proper engineering of the transistor, and SOI will offer still more speed performance due to the floating-body effect. Targeting low power is even more favorable, since SOI can deliver the same speed performance while lowering the power supply voltage.
Design issues associated with switching from SOI to strained SOI are the same as those tied to switching from bulk to strained silicon. For both bulk silicon and SOI, electrical characterization of the cells must be redone to account for the extra drive current created by changing the mobility parameters in the Spice software models. Partially depleted SOI is a bit more complex due to the history effect; propagation delay depends on the history of the input signals. Proven Spice models, already used for designing with partially depleted SOI, are still needed for fully depleted SOI.
The right intellectual property (IP) allows circuit designers to keep using their established standard design flow. The extra complexity due to the modified layout and electrical behavior of the SOI transistors is already included in the EDA views feeding the circuit design tools (synthesis, timing analysis, place and route). The designer may then benefit from the higher density of the cells (between 10 and 20 percent), the higher speed (up to 25 percent) and the lower power consumption (down to 50 percent). These benefits more than justify the extra work needed to build SOI IP.
Jean-Luc Pelloie is president and chief scientist at Soisic (Grenoble, France)