How many 90-nanometer tapeouts have there been to date, and which IC implementation tool vendors have been primarily responsible?
How many 90-nanometer tapeouts have there been to date, and which IC implementation tool vendors have been primarily responsible? The short answer to the first question is "not very many," and to the second question, "all of them."
In a 90-nm tapeout discussion in a recent E-Mail Synopsys Users Group mailing, consultant Kahoo Goyal Edson said she believes there have been around 160 of the 90-nm designs to date, of which about half have taped out. Of these 80 or so tapeouts, she speculated, 30 to 40 have been done in a Cadence flow, 30 to 40 in a Synopsys flow and fewer than 10 in a Magma flow. But, she noted, the real story is hard to find.
Bryan Lewis, semiconductor analyst at Gartner Dataquest, said he was able to find fewer than fifty 90-nm tapeouts last year and expects about 275 this year. He said Edson's guesstimate of 160 designs to date is "in the ballpark."
But which EDA vendors? Gary Smith, chief EDA analyst at Gartner Dataquest, said the most popular 90-nm flow appears to include Cadence Design Systems' First Encounter floor planner and CeltIC signal-integrity tool, with Magma Design Automation doing block-level design and Synopsys' Galaxy platform handling the remainder.
Representatives of Synopsys and Cadence agreed that Edson's estimate of 160 designs and 80 tapeouts sounds about right. Synopsys claims that all of these 90-nm designs used Synopsys tools for synthesis, extraction and timing analysis, and half used Synopsys for place and route, with Cadence and Magma dividing the other half.
Cadence claims that about forty 90-nm tapeouts have used Cadence's netlist-to-GDSII flow, and at least a few have used Cadence synthesis. Magma claims to have been involved in at least twenty 90-nm tapeouts, and not just for block-level design.
The real story is that big EDA customers shop around. Takashi Yoshimori, technology executive at Toshiba, said his company has done more than ten 90-nm tapeouts to date. He noted that Toshiba's 90-nm flow may include the use of Synopsys' Apollo or Astro, Cadence's SoC Encounter or Magma's Blast Fusion, depending on the project.
Watch now for Cadence, Synopsys and Magma to each put out press releases stating that Toshiba has "standardized" on its implementation flow for 90-nm designs.
Richard Goering is managing editor of Design Automation for EE Times.