A month ago, it looked like things might be pretty dull at the Design Automation Conference this year.
A month ago, it looked like things might be pretty dull at the Design Automation Conference this year. Just within the past few weeks, however, new companies and products have emerged that promise to make things interesting as DAC convenes in San Diego June 7-11.
Look for new activity in the IC implementation area, which includes RTL-to-GDSII tool suites. Synopsys, Cadence and Magma may not have a lock on this market after all. Newcomer Sierra Design Automation this week will introduce Pinnacle, a physical synthesis tool that claims to handle 10 million gates flat in an overnight run on a 32-bit machine. Pinnacle claims equivalent or better quality of results than existing physical synthesis tools, which handle much smaller blocks.
Sierra doesn't have RTL synthesis or detailed routing, but it does have plans for the latter. With a CTO who led R&D efforts for Synopsys' Design Compiler and Physical Compiler, the company should be taken seriously.
It is perhaps no coincidence that Synopsys this week will announce Galaxy 2004, which claims a twofold run-time speedup and 40 percent capacity gain for physical synthesis.
In the verification area, startup Lighthouse Design Automation is introducing elements of what Dataquest calls the intelligent testbench. Lighthouse's inFact product line synthesizes testbenches, claiming to reduce development time by up to 80 percent. Meanwhile, 2003 startup Jasper Design Automation is unveiling what it calls a "provably correct design" methodology.
Power and signal integrity, huge challenges at 90 nanometers, will take center stage in many announcements. Magma, for example, has introduced a Blast Power option; Sigrity is expanding from pc-board signal integrity into chips; Sequence is partnering with startup Golden Gate on power grid design; and Apache is adding dynamic-power noise analysis to Redhawk-SDL.
What about electronic system-level (ESL) design, which was a hot topic last year? This year, the question is whether small companies like Forte, Summit, CoWare and Celoxica can forge a market that Cadence and Synopsys have largely abandoned.
IC implementation, verification, power and ESL will all show up in the DAC technical program as well. See www.dac.com for details.
Richard Goering is managing editor of Design Automation for EE Times.