While the semiconductor industry begins a cautious rebound, pundits and observers are carefully watching and trying to predict how it will manage the move toward reaggregation.
While the semiconductor industry begins a cautious rebound, pundits and observers are carefully watching and trying to predict how it will manage the move toward reaggregation. The industry appears to be moving back to an ASIC or ASIC-like model because it's too expensive and too risky to go to a customer-owned-tooling model.
Perhaps a more interesting trend is the struggle that supply-side companies and design teams have with the implications of Moore's Law-both technically and economically-while trying to continue to double the number of transistors on a chip roughly every 18 months.
Those trends-the growth of the intellectual-property industry, the fabless model, the need for reaggregation, the cost of design-all confirm that the benefits of Moore's Law for an information-based economy are worth sustaining. The trick is to reduce complexity and cost, and the trend toward reaggregation is another way of saying "automation."
Throughout my career, I've watched these trends and moved accordingly. I left the automatic test equipment sector for electronic design automation, then IP, to capitalize on those transitions and the industry's disaggregation.
After my stint in the IP market sector, I concluded that EDA and IP will reaggregate. It will not be a complete reaggregation but will cause intersection points where automation is missing.
Libraries are a perfect example. Historically, the performance of back-end tools was tied to the optimization of cell libraries. That's why EDA players Mentor Graphics and Synopsys had library businesses.
A new reaggregation point is at the front end of the design cycle because design teams need more automation to deal with the myriad decisions that need to be made at 130 nanometers and below.
Several factors are driving this. For example, most of the chip will be existing IP that will be from a third party. Finding it and determining the chip's specifications, availability and design implications are time-consuming and risky tasks. The number of process and technology choices is exploding, and each one must be checked against all the IP. The cost-in time, money or both-of making a wrong decision is driving analysis paralysis. Existing methods like Excel spreadsheets, pencil and paper and human time are inadequate to the task.
Thus, the need is great for a front-end system that merges EDA with IP data, estimation and modeling technology. Such a system could reduce the time and risk involved in making the hundreds of decisions required to get a chip into production and have it meet specs. It would let the chip industry reap the benefits of Moore's Law for a while longer.
Vin Ratford is president of Giga Scale Integration Corp. (Cupertino, Calif.).