The evolution of microprocessor architecture through the 1970s, 1980s and 1990s can be viewed as a process of reusing techniques first implemented in IBM mainframes in the 1960s. Just as we are running out of ideas to steal, the need for new high-performance microarchitectures is ending.
Two recent Intel announcements underscore this denouement. The company canceled development of its Tejas processor-a Pentium 4 derivative and not a truly new microarchitecture-in favor of dual-CPU chips. Intel now plans to increase performance using more CPUs, not more powerful CPUs.
A shift to multiple CPUs per chip reduces the need to rearchitect the CPU itself. Need more performance? Just add CPUs.
Intel is also moving away from clock speed as the key performance metric, instead labeling its chips with BMW-like model numbers. This change, combined with Tejas' rumored heat problems, represents a repudiation of the speed-at-any-cost approach of the Pentium 4 microarchitecture.
Clearly, power dissipation is becoming the most important metric in designing processors.
In the embedded market, where power dissipation has always been more important than showy clock speeds, CPU designers remain focused on shorter pipelines, simple scalar or two-issue superscalar designs, and little or no instruction reordering or speculative execution.
Network processors and other embedded processors already rely on multiple CPUs to raise performance. This approach is more power-efficient than trying to squeeze more performance from one large CPU. In PCs and servers, however, many applications can't use more than one CPU. To accommodate software developers, CPU architects have spent years doggedly increasing single-CPU performance. As the limits of this approach become apparent, however, software developers must rewrite their code so it can be divided among multiple CPUs.
The opportunities to design a new microarchitecture from scratch are few. Most CPU architects are simply extending existing designs, trying to wring out a bit more performance per watt. With little need for new microarchitectures, processor designers now focus on the trade-offs in memory and I/O bandwidth, on-chip memory and peripherals, power and cost.
Linley Gwennap is founder and principal analyst of The Linley Group and co-author of "A Guide to Storage Networking Silicon" (www.linleygroup.com/npu).