Now that the Design Automation Conference is over, it's time for a quick look at highlights. Significant changes-and questions-emerged in design for manufacturability (DFM), electronic system-level (ESL) design, and design and verification languages.
Overall, this year's DAC seemed more optimistic than those from the past few years. In its annual pre-conference briefing, Gartner Dataquest predicted 11.8 percent growth in EDA product revenues in 2004, with growth returning to 18 to 20 percent annually after that.
If there is an overriding theme, it is probably this: DFM is a problem, and chip designers who delve below 100 nm will have to deal with it. Both DAC keynotes raised the subject, as did several panels and presentations. One DFM technique is resolution enhancement technology (RET), one of the fastest-growing areas in EDA.
The need for yield prediction and analysis is growing, and startups are preparing yield optimization tools that can alter chip layouts, though area and performance trade-offs are likely.
Meanwhile, power management and signal-integrity challenges escalate. The question is whether DFM, power and signal integrity are so daunting that only foundries, and a handful of exceptionally well-equipped power users, will be able to complete 90- and 65-nm designs.
In ESL, several companies are offering C-language synthesis tools. That fills a gap in the ESL design methodology, but will people actually use the tools? SystemC appears to have settled into a niche as a modeling and verification language but isn't used much for design.
Speaking of languages, System-Verilog is gaining momentum, with nearly 30 EDA vendors rolling out product support plans at DAC. Many are embracing its assertion and testbench features. Controversy remains over Accellera's decision to seek a separate IEEE standard, but SystemVerilog is becoming a reality.
Physical synthesis has become a battleground, with new entries from startup Sierra Design Automation as well as Cadence Design Systems. Nobody has a lock on what may be EDA's crown jewel from a revenue standpoint: the RTL-to-GDSII implementation suite. But unless DFM, power management and signal integrity optimization are brought into that flow, not many design teams will be able to use it.
Richard Goering is managing editor of Design Automation for EE Times.