It's hard to be terribly optimistic about CMOS device scaling, particularly as power consumption replaces raw performance as the chief concern.
At the Symposium on VLSI Technology last month, some of the industry's best brains managed a wan form of optimism-concluding that all will turn out well, somehow, in the face of stupendous odds.
Thomas Skotnicki, advanced devices program manager at ST Microelectronics, analyzed scaling challenges. One takeaway: operating voltages, or Vdd, traditionally have been kept at five times the threshold voltage (Vth). It is hard to imagine how Vth can be reduced much further, Skotnicki said, without an "explosion" in off-current.
Chenming Hu, a University of California at Berkeley professor, listed technology "boosters" that can advance CMOS scaling: process-induced strained silicon has been implemented at many companies. As gate lengths shrink and dopants are kept out of the channel, carrier mobilities could speed up further because of ballistic transport. Carbon nanotubes have 10 times the current density of silicon nanowires, Hu said.
Fully depleted CMOS may be implemented on SOI substrates with "global" strain induced from a silicon-germanium layer. Multi-gate devices, such as FinFETs, could take advantage of FD-SOI.
Engineered substrates could offer different crystal orientations for the NFETs and PFETs. Later, that approach could include germanium deposited on silicon substrates, capitalizing on the faster PMOS performance in germanium. Even compound semiconductors could be made on silicon substrates, though Motorola's attempt to do so failed a couple of years ago.
Then there is the difficult search for the right combination of metal gate electrodes that work well with high-k materials. Skotnicki raised doubts that today's high-k materials will deliver the performance needed for high-performance ICs; others fear that high-k dielectrics won't be ready in time for the low-standby current transistors.
As Toshihiro Sugii of Fujitsu Ltd. noted, "To share the pain, a number of these technology boosters will be needed. Meanwhile, each technology node lasts slightly longer."
Hu wonders whether cost improvements will be possible with such complex processes. "We have not put enough innovation into cost containment," he warned, adding that the semiconductor industry has always "come up with innovations just in the nick of time."
David Lammers covers SoC process equipment. Contact him at email@example.com.