Although low-k dielectrics with k values in the range of 3.0 have already been introduced into back-end-of-the-line pilot production, the ultimate ultra-low-k material that complies with all the requirements of the future microelectronics industry has not yet been found. The race between spin-on and chemical vapor deposition-deposited materials-organic, inorganic or a hybrid combination-is still ongoing.
Historically, spin-on materials present an important advantage over CVD materials: the ability to introduce a high degree of porosity in the films (up to 50 percent and more), reaching k values as low as 2.0. But problems with integrating ultralow-k materials have caused a delay of two device generations in bringing low-k dielectrics into production. Hence, CVD materials with "moderate" low-k values (2.8 to 2.4) have regained considerable attention.
Both the spin-on and CVD low-k approaches present numerous integration challenges compared with conventional SiO2, which is mechanically tough, relatively inert, thermally stable and easy to deposit. A series of critical material properties for low-k materials determines their integratability in damascene processes.
Mechanical strength and thermal stability are of primary importance. They decide whether a material can withstand chemical-mechanical polishing or survive wire-bonding and packaging processes. Due to their porosity, low-k materials in general have lower mechanical strength compared with SiO2. As a rule, spin-on-deposited dielectric materials show a relatively lower degree of cross-linking and thus lower mechanical strength than CVD-deposited films. CVD films also show better thermal stability.
The pore structure-including size, porosity and connectivity-is another key issue. Porosity determines the k value of the dielectric, but the pore structure and distribution also influence other basic material properties and the integratability of the dielectric films. A number of important process interactions such as interaction with plasmas, swelling of low-k dielectric films in liquid media and thin-film deposition on porous dielec-trics especially pose problems for all films with a high degree of subtractive porosity. This is because in most cases the introduction of a high porous volume in the dielectric films goes together with the presence of a high degree of meso-connectivity among the pores. Any exposure of the dielectric will lead to contamination of the dielectric.
Spin-on and CVD dielectrics have pros and cons. But as chip makers prepare to put low-k dielectrics into production, manufacturability, tool productivity and cost of ownership become increasingly important. Those issues have increased interest in CVD materials. First, CVD allows a simpler process sequence and many companies have CVD tools at their disposal. Spin-on integration still requires CVD-based dielectrics for hard-mask and barrier applications, for example. A spin-on dielectric flow therefore demands CVD tools in addition to the required spin-on coaters and furnace. Also, the chemicals needed for spin-on materials cost far more than the CVD precursors.
But the real question is how to design a material that has both maximum porosity and a pore structure that can be sealed. And, last but not least, the material must have the right properties for mechanical and electrical reliability. With this in view, both CVD and spin-on-deposited low-k materials are being explored, with a special focus on materials with small pores and high porosity. Today, low-k material suppliers, both for spin-on and CVD dielectric films, are working out solutions to extend the deposition technique in which they have the most expertise.
Spin-on materials with mechanical properties as good as CVD films are becoming available, as are CVD films with k values approaching 2.0. Differences are becoming less pronounced.
Karen Maex is strategic research coordinator of the Silicon Process and Device Technology division at the Interuniversity Microelectronics Consortium (IMEC; Leuven, Belgium).