For some time, the industry has been nervously eyeing two seemingly unrelated issues: the enormous build-out of fab capacity in China and the continuing struggles with 90-nanometer processes.
For some time, the industry has been nervously eyeing two seemingly unrelated issues: the enormous build-out of fab capacity in China and the continuing struggles with 90-nanometer processes. The two might seem independent, but in at least one respect, they are converging.
Trend No. 1 is all about cost. Enormous fab capacity is being planned in China. If it all came online, some analysts said, it would undermine world wafer prices. But other pundits said no, the capacity was all at 180 or 150 nm, and it was intended for Chinese domestic markets-don't worry, world.
But a funny thing is happening on the way to the finale. Just as predicted, the Chinese fabs are beginning to come online with older-yet nonetheless highly competent-processes. Breaking with the script, the big fabs seem to have just as much interest in the rest of the world as they have in their domestic market. Word on the street is that a 180-nm, six-metal, 200-mm wafer is going for $800 at the moment. Prices like that could shake the foundations of the foundry market.
But it's all in obsolete processes, right? That brings up the other trend. Reports from early designs confirm that, on paper, 90-nm processes are fast. In fact, however, by the time you account for power management, the timing slack eaten up by signal-integrity issues and process variations and the design rules necessary for good yield, the performance gains from 90-nm CMOS are not that impressive. One design manager described the result as something like a 110-nm process. And at their current immature stage, designs are very hard and somewhat risky. Bottom line: Right now 90 nm may have more to offer in density than in performance, and nothing at all to offer to the power-conscious or the thinly funded.
Put these two together, and you have a growing number of design teams looking at their architectural designs to see whether-just maybe-a change in architecture could make it possible to meet the design requirements in those incredibly cheap 180- and 150-nm processes. A little more parallelism, a better set of libraries, a hardwired accelerator here and there can make a difference. And that could change a lot in the design world.
Ron Wilson covers microprocessors, programmable/reconfigurable logic and the chip design process. He can be reached at firstname.lastname@example.org.