SystemVerilog is being used today to develop powerful constrained-random, coverage-driven automated testbench environments with reusable and extensible components. The focus on coverage provides the metrics necessary for integration into a full plan-to-closure verification methodology. Constrained-random, coverage-driven testbenches are essential not only at the full-chip level but also at the "cluster" level for major chip subsystems.
At the block level, logic designers can also benefit from testbench automation. However, many designers do not come from a software background and may be reluctant to learn class-based, object-oriented techniques. Fortunately, SystemVerilog also has the features to support a module-based approach that does not require any knowledge of object-oriented programming. This intuitive and easy-to-adopt approach is proving quite effective at enabling logic designers to build constrained-random, coverage-driven testbenches to perform early verification.
Although somewhat less reusable and extensible than a pure class-based approach, module-based methodology is also getting significant use by verification engineers at the cluster and chip level, particularly in teams where logic designers and verification engineers work closely together. Purely class-based SystemVerilog methodology, on the other hand, is quite attractive to dedicated verification teams that don't overlap with logic design teams.
The advantages of SystemVerilog for verification engineers are clear. But logic designers also benefit from SystemVerilog's powerful and expressive RTL constructs, assertions for formal analysis and simulation, and support for automated block-level testbenches. Design with verification leverages all aspects of the language to find bugs efficiently, early in the project timeline. That helps the entire chip development team, while allowing logic designers to sleep easier at night and get their weekends back.
Michal Siwinski is a solutions marketing group director at Cadence Design Systems Inc.