The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts from proven verification languages, property/assertion languages, and even object-oriented programming languages. With its many new features, SystemVerilog can appear a bit daunting in its entirety.
Partly for that reason, and partly because of the history of the donations that influenced the standard, it is common to divide the new features of SystemVerilog into three categories: assertion constructs, design constructs and verification constructs. This categorization has some merit, at least from a syntax perspective, but it can be misleading, in that logic designers use more than the design constructs, and verification engineers use more than the verification constructs.
Perhaps it makes more sense to think of SystemVerilog with overlapping categories corresponding to the different user communities: system architects, logic designers, verification engineers and so forth. In this context, it is clear that a significant portion of the language is applicable to logic designers.
SystemVerilog is closely linked to the continuing evolution from "design for verification" to "design with verification." The former phrase implies that the logic designers are doing a favor for the verification team; the latter entails integration of appropriate verification techniques into the RTL design process. Most of these techniques are not new, but the rich feature set and wide availability of SystemVerilog are accelerating adoption of design with verification.
Assertion specification is an excellent example. The value of assertions has been established for many years, but assertion usage has risen dramatically since SystemVerilog appeared. The language provides a rich set of constructs and features in the SystemVerilog Assertions (SVA) subset. In addition, since many design and verification tools support SVA, it's easy for engineers to try assertion-based verification techniques.
The value of assertions is especially high for logic designers. Assertions document designers' intent, reducing calls from colleagues attempting to reuse the designs on other projects. Assertions supplement the limited error checking done in most designer block-level testbenches. They also work with formal analysis, making design bring-up more efficient and catching bugs earlier in the project.
In chip-level simulation, acceleration, and emulation, assertions detect bugs at their sources and greatly reduce the amount of time that logic designers, verification teams, and system validation teams spend debugging. In addition to the designer assertions, verification teams often specify additional assertions to help with coverage-driven verification goals.
The design constructs in SystemVerilog allow logic designers to write RTL code that is inherently cleaner (fewer bugs) and more verifiable. For example, the "interface" construct eliminates a whole category of cut-and-paste errors that used to occur whenever I/O signals were changed in the design. Design constructs also help designers and verification engineers write cleaner code for high-level models and testbenches.
Speaking of testbenches, SystemVerilog has many constructs and features that provide much more capability than Verilog and VHDL. Many concepts from object-oriented programming, such as classes, methods and encapsulation, are well supported in SystemVerilog. Verification engineers familiar with verification languages such as e or SystemC will find many similar concepts available in SystemVerilog.