As we get down to 65-, 45- and 32-nanometer designs that are increasingly complex and harder to manufacture, we're assuredly going to run into design closure and manufacturability problems--to the extent that we'll effectively shut down chip design if we continue using our current design flows.
These flows came into being in the 1980s, and we've been adding analysis and verification tools to them ever since, tweaking the design flow to fix problems. The result is a 20-plus-year-old design flow methodology that's burdened like an old boat encrusted with barnacles. This ship's going to sink.
What's the fix? A fundamental remodeling of the EDA design flow. Rather than check, analyze, verify and repair ad nauseam, we need to move to a new methodology that arms chip designers with predictable, accurate information, emanating from new tools created and tuned for tighter manufacturing process tolerances.
In the traditional, corner-method design flow philosophy, the corners cover all possible process, voltage and temperature conditions, whether realistic or not. Up to 90 nm, and for slow frequency devices, the corner approach was "good enough."
At 65 nm, however, process tolerances and their margins are being reduced to a point that the corner characterization and static timing analysis flow can no longer accurately predict silicon performance. Random and systematic process variations play a much larger role in electrical performance. At 65 nm, if a designer uses corner methods, the result will be many more design spins, greater cost overruns and even longer production delays.
The better approach to predicting the impact of random and systematic variation is to create a design flow that accounts for statistical variation. The semiconductor manufacturing process is statistically controlled, with each process step controlled by specified limits; stay between the lines, and you get consistency and high yields. For accurate and predictable timing closure, the "lines" need to be changed from corner descriptions to statistical distributions.