Hot papers from this year's VLSI Technology Symposium include three nonvolatile memory advancements: Toshiba' BiCS Flash, Samsung's vertical-stacked transistor structures and Hitachi's PCRAM. Two papers on advanced logic processes include: Intel's" High-k/Metal Gate Stacks" and IBM's "32nm SOI CMOS with Highk/ Metal Gate."
KANATA, Ontario I always enjoy looking through the advance programs of the Big Three chip conferences--IEDM, ISSCC and VLSI. This year is no exception. The next big event is the 2009 Symposia on VLSI Technology and Circuits scheduled next week in Kyoto, Japan.
Here are my top five tech papers from the Technology Symposium, a pillar of the upcoming VLSI Symposia. I leave the papers from the Circuits Symposium (another pillar of the VLSI Symposia) to someone with expertise in that area. Please note that I made no attempt to rank the five best papers. They are mentioned in no particular order.
We are getting close to the tipping point for solid-state drives. I think it is more than hype as the next couple of years are bound to prove. So it should be no surprise that this list is biased toward nonvolatile memory.
If solid-state memories are to displace spinning disk technology, they need to place amongst the densest storage media, and move into terabyte territory.
In nonvolatile, it appears that the field has narrowed to two main competitors, Toshiba and Samsung, vying to replace traditional floating-gate NAND flash.
There is an option from the NAND flash camp, and it will be a form of cell stacking or 3-D memory.
Toshiba's work in this field is described in "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices" which will be presented in Session 7 "Highlights" on Tuesday (June 16). BiCS is short for "Bit Cost Scalable."
Toshiba's flash paper made it to the highlight session, but Samsung took three out of four spots in the NAND Flash Memory Session. Until now, it appeared that Samsung's approach to increasing NAND flash density was to simply (okay, I obviously don't work in a fab) stack up many levels of conventional devices.
In that integration scheme, many levels of NAND flash arrays are patterned, one on top of the other, in a way resembling the die stacking in packages common today.
Samsung could be abandoning that approach, or at least diverting resources to a concept that is closer to Toshiba's paper about its pipe-shaped BiCS flash.
The Samsung paper is first up during Session 10A on NAND Flash Memory. "Novel Vertical-Stacked-Array-Transistor (VSAT) for Ultra-High-Density and Cost-Effective NAND Flash Memory Devices and SSD (Solid State Drive)" is the product of collaborative research with UCLA.
The second paper in this track is titled, "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage," and seems to address features of the same technology described in the first paper. Both papers mention vertical-stacked transistor structures and offer a new flavor for Samsung.
This technology is closer to what Toshiba has been discussing for awhile, and appears to be where flash technology will converge in the future.