Reports of low yields on its 40-nm process technology have placed TSMC in the technology spotlight.
We've heard a lot about TSMC's difficulty improving yield on its 40-nm process. In this article, I review the speculation in the news and take a look at what might be preventing the foundry from achieving acceptable yield.
There has been a lot of talk recently about horribly low yield on GPU's manufactured on TSMC's cutting edge 40-nm process. It appears to originate from an FBR Capital Markets report by Mehdi Hosseini in which EE Times semiconductor editor Mark LaPedus quoted Hosseini as saying, "We believe yields are as low as 20 percent to 30 percent." The two graphics chip companies and large TSMC customer are rather unhappy about the situation, and TSMC has admitted although reservedly that the yield ramp for 40 nm is "challenging."
According to the report, Hosseini also speculated that Morris Chang's return to running day-to-day operations at the foundry was the result of the low yields on 40 nm. It's unlikely that anyone really doubted Dr. Rick Tsai's ability to manage through this situation, though. More likely, it's simply an attempt to avoid panic on the markets.
As one of my colleague's put it, this is a natural situation for an ASIC design in a new process. Natural though it may have been at Nortel, how can you make a business out of junking three-quarters of your product? Just look at where Nortel is today. I'm just kidding of course. Nortel management didn't need technical failures to bring that company down.
My question was and is: "What does a fabless company gain by jumping onto a new node before it's mature?" Another trusted colleague suggested that it is Nvidia's customers who drive this decision. They can leverage the idea that a process shrink will reduce production costs for the Nvidia GPU's " perhaps not today but down the road. Of course, they are playing dumb on the cost issue to get better performance than they would if Nvidia just waited until it was sure TSMC could provide a more reasonable number of working die per wafer.
This seems to fit with DigiTimes reports out of Nvidia about the transitioning to 40 nm. Nvidia's current plan is to move to 40 nm only for OEM devices and will switch its own branded products sometime later.
But so far no one has addressed the possible sources of the yield ramp "challenges." After polling colleagues internally as well as through external networks like LinkedIn, I can narrow it down to the four most likely causes:
Introduction of e-SiGe source/drains
Mechanical stability (or lack thereof) of the low-k interconnect stack
Particle control is always an issue, so that one is a given. Nobody I have talked to has any inside information on that, so there's really no way to know. Similarly, no none has any solid data regarding TSMC employing e-SiGe for the first time.
But analysis of two very different types of chip built on the TSMC 40nm leads to speculation that the difficulties lie on the back end. Xu Chang, Senior Process Analyst at Semiconductor Insights, has thoroughly investigated the Altera Stratix IV as well as the Nvidia GPU which were both built on the 40nm node. There are slight differences in the two flavors of TSMC 40nm considering the applications of the two devices. The Altera FPGA employs looser design rules with longer gate lengths and thicker gate oxides. However, the die is nearly three times the size (almost 400 square millimeters) which increases the chances of a killer particle defect. The smaller GPU is designed for higher performance and must suffer the possibility of reduced yield as a result.