What does it take to make SoC designs optimally profitable?
Engineering executives at chip vendors and electronic equipment makers are grappling with this question in the midst of a global economic downturn and as the ability to offer the best products at the most attractive prices becomes a major competitive weapon of choice for many in the industry.
On Wednesday (Sept. 16), the electronic community would have another chance to explore the various strands of the issues surrounding the increasing cost of SoC designs at the EE Times SoC Virtual Conference System-on-Chip: Designing Next-Generation SoCs.
It may not be easy for engineers and industry executives to agree on a single solution on how to optimize the SoC design process because there are various arguments supporting the two conflicting positions: the FPGA-based approach and the ASIC-based approach.
The differences extend well beyond polemics. For the industry, there are significant differences amongst the proponents of the FPGA vs. ASICs approaches. Well-entrenched interests are advocating differing options even as profit motives drive decisions that design engineers must wish they can take solely on the basis of the technologies involved.
What's clear across the industry is that SoC costs are on the rise and the potential advantages to the companies that get their cost structures right are immense, depending, of course, on the applications and the market segment.
Are the facts as clear cut as each sides of the divide would have you believe or are there nuances to be discerned in the process? What should management and design engineers focus upon as they select an approach and would these help them win in the market place?
Jacques Benkoski, a Venture Partner at USVP, and executive chairman of the board of directors at Synfora, believes programmability is now a game changer but there are other individuals who have differing opinions.
What do you think? Join the conversation and let us know where you stand.