Virtual Conference keynoter claims it may be impossible to utilize all the available transistors on a chip.
Moore's Law keeps marching relentlessly forward, thanks to engineers conjuring up increasingly clever tricks to push back against the laws of physics. According to ARM, in the last seven years mobile phones have shown a 50X improvement in talk-time per gram of battery, while at the same time taking on new computational tasks that only recently appeared on desktop computers, such as 3D graphics, audio/video, internet access, and gaming. Now you can use your Blackberry to watch streaming video from YouTube or play interactive online games while pretending to check your email.
Still, there's trouble in paradise. This Thursday, ARM's CTO Mike Muller will deliver the keynote address at EE Times' Designing with ARM virtual conference. According to Mike, despite process scaling down to 11 nm, fixed power budgets may soon make it impossible to utilize all the available transistors on a chip. Without fresh innovations, designers could find themselves at some point in an era of "dark silicon," able to build dense devices they cannot afford to power.
Muller makes his argument with the following numbers: Compared to a 45-nm die, 22 nm will enable a 4X die shrink; 11 nm, 16X. Again taking 45 nm as the reference point, the peak frequency at 22 nm can increase 1.6X and at 11 nm, 2.4X. All well and good. However, while power consumption may remain constant at 22 nm vs. 45 nm, at 11 nm it drops to 0.6. All this means that at a 45-nm power budget, at 22 nm only 25% of the silicon is exploitable and only 10% is usable at 11 nm. Clearly this isn't an acceptable trend line.
In his keynote Mike will detail both tactics and strategies for lighting up what would otherwise be "dark silicon." Silicon on insulator (SoI) will play a big role—the first ARM-based 22nm SoI chips taped out last October; SoI goes a long way toward addressing the leakage problem at smaller geometries. Energy-efficient and robust high-density memories will facilitate reduced operating and retention voltages. 3D silicon integration (3D ICs) will enable high levels of energy efficiency and performance improvements.
Other recommendations and predictions: Muller sees Neon++ as the future of vector processing, improving single-threaded performance and extending Neon's reach to new application domains. Stream programming on the GPU—using the OpenCL programming model—makes possible high-throughput computations on floating-point intensive applications. Mike sees MP++ as "the future of multi-core scalability" and in his talk goes into some of the architectural implications and scalable coherence techniques. He will also discuss the evolution of the SoC interconnect and some of the ins and outs of sub- and near-threshold circuit design.
On the strategy side Muller explains a new approach to dynamic voltage scaling, referred to as Razor, which is based on dynamic detection and correction of speed path failures in digital designs. The key idea of Razor is to tune the supply voltage by monitoring the error rate during operation. Muller proposes a combination of circuit and architectural techniques for low-cost, in-situ error detection and correction of delay failures.