There is a paradox brewing in the layout of integrated circuit designs at nanometer nodes. IC design teams are choosing between layout automation vs. full custom design techniques.
While the automated layout tools seem fast, engineers may grow old fixing timing, power and yield problems on the back end of the flow. Meanwhile, full custom tools give designers more control over custom digital and mixed-signal circuit layouts, but the lack of automation can make project completion seem light-years away.
The nanoscale IC design paradox is that designers need both hands-on custom control and high-speed automation performance.
Generally, large IC designs are created using automated place-and-route (APR) tools. The larger the design, the more the speed and confidence of APR tools outweigh the potential compromises in area or performance.
Custom IC layout methodologies are usually reserved for analog, performance-critical digital or mixed-signal blocks. This separation of responsibilities has worked well for years and is reflected in organizational structures separating digital and mixed-signal designers, and disconnected tool flows between standard digital (automated) and everything else (custom).
However, at nanoscale nodes processes 45nm and smaller things change. Design requirements and economies of scale are forcing the combination of custom analog circuits with digital logic onto mixed-signal chips.
Additionally, critical paths in digital layouts are sometimes best resolved through the insertion of custom digital circuits.
In a real sense, all nanometer-scale chips are becoming custom designs. As a result, layout flows must change to provide interoperability between traditionally separate tools.
With transistor counts in the tens of millions, and clock speed requirements exceeding 2GHz, nanoscale designs represent a challenge to traditional APR tools on sheer capacity alone. But process design rules of nanoscale processes are also incredibly complex, choking the analysis engines of past-generation routing tools.
Spot application of custom design can augment APR tools, but with one tool working at odds against another, the multi-tool approach is often counter-productive.
Design integrity, along with hierarchy and connectivity, is too often lost in transition between the tools. APR re-routes circuits laid by hand, while the custom insertion creates space roadblocks and parasitic challenges for the auto-router. It's no wonder that layout and chip finishing can become the gating factor for IC tapeouts.
At advanced nodes, new routing engines are required, specifically designed to handle the complexities and capacity of nanoscale design. Tools in this flow must be truly interoperable.
It's no longer acceptable to cobble together one tool for custom routing, and another to handle the bulk digital routes. Integrated, semi-automated flows can deliver the best of both worlds the hands-on control of custom design for fine tuning design timing and power, and intelligent automation with the raw speed needed to lay down millions of non-critical routes.
High-performance custom design requires best-in-class tool features working in concert: cell placement, automated routing, interactive custom routing, design rule checkers, parasitic extraction, timing analysis, power analysis and yield enhancement tools to name a few.
Custom design with integrated analysis will enable true "what-if" exploration of custom point design, with fast automated routing completing the layout. The key to making these tools work together interactively is database interoperability.
In recent years, powerful IC layout and analysis tools have been built on the OpenAccess (OA) database from the Silicon Integration Initiative (Si2) standards organization.
The OA database allows different tools to operate on the same in-memory representation of the design, enabling the seamless interaction of tools even those from different vendors as if they were a single design tool.
Using OA, and other design tool standards such as Tcl, Python and IPL, interoperable tools deliver a new path for nanoscale IC design layout, chip finishing and assembly. Such tools have already been shown to drastically shorten IC layout time.
For some nanoscale design benchmarks, routing problems that had previously taken six weeks were resolved in literally minutes.
Phil Bishop has over 25 years of experience in high technology industries.